component
MCP2542WFD-E
Public Made by Adomby adom
Microchip Tech CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownMCP2542WFD-E
Microchip Tech · CAN ICs · SOIC-8
MCP2542WFD-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input from the CAN controller; low drives CANH/CANL Dominant, high Recessive, with an internal nominal 33 kΩ pull-up to VIO. |
| 2 | VSS | power_in | Ground supply pin. |
| 3 | VDD | power_in | Positive supply voltage pin supplying the transmitter and receiver, including the wake-up receiver. |
| 4 | RXD | output | CMOS-compatible receive data output driven to VIO, high when the bus is Recessive and low when Dominant. |
| 5 | VIO | power_in | Digital I/O supply pin for TXD, RXD and STBY, enabling interfacing to MCUs with 1.8V to 5V I/O. |
| 6 | CANL | bidirectional | CAN Low-level voltage I/O driving the low side of the differential bus and tied to the receive comparator; disconnects from the bus when unpowered. |
| 7 | CANH | bidirectional | CAN High-level voltage I/O driving the high side of the differential bus and tied to the receive comparator; disconnects from the bus when unpowered. |
| 8 | STBY | input | Standby mode input selecting Normal or Standby mode, with an internal MOS pull-up to VIO (typically 660 kΩ at 5V, 1.1 MΩ at 3.3V, 4.4 MΩ at 1.8V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage | VDD | 7 | V | 12 | |||
| VIO supply voltage | VIO | 7 | V | 12 | |||
| DC voltage at CANH and CANL | -58 | 58 | V | 12 | |||
| Transient voltage on CANH and CANL | -150 | 100 | V | ISO-7637 (Figure 2-5) | 12 | ||
| Differential bus input voltage | VDIFF(I) | -5 | 10 | V | t = 60 days, continuous | 12 | |
| Storage temperature | -55 | 150 | °C | 12 | |||
| Operating ambient temperature | -40 | 150 | °C | 12 | |||
| Virtual junction temperature | TVJ | -40 | 190 | °C | IEC 60747-1 | 12 | |
| Soldering temperature of leads | 300 | °C | 10 seconds | 12 | |||
| Supply voltage range VDD | VDD | 4.5 | 5.5 | V | 13 | ||
| Supply current, recessive | IDD | 2.5 | 5 | mA | Recessive, VTXD = VDD | 13 | |
| Supply current, dominant | IDD | 55 | 70 | mA | Dominant, VTXD = 0V | 13 | |
| Standby current | IDDS | 4 | 16 | µA | MCP2542FD and MCP2542WFD, includes IIO | 13 | |
| Maximum supply current | IDDMAX | 95 | 140 | mA | Fault condition: VTXD = VSS, VCANH = VCANL = -5V to +18V (Note 1) | 13 | |
| VDD POR high level | VPORH | 3 | 3.95 | V | Note 1 | 13 | |
| VDD POR low level | VPORL | 1 | 2 | 3.2 | V | Note 1 | 13 |
| VDD POR hysteresis | VPORD | 0.2 | 0.9 | 2 | V | Note 1 | 13 |
| VDD UV high level | VUVH | 4 | 4.25 | 4.4 | V | 13 | |
| VDD UV low level | VUVL | 3.6 | 3.8 | 4 | V | 13 | |
| UV comparator hysteresis | VUVD | 0.4 | V | Note 1 | 13 | ||
| Digital supply voltage range | VIO | 1.7 | 5.5 | V | 13 | ||
| Supply current on VIO, recessive | IIO | 7 | 20 | µA | Recessive, VTXD = VIO | 13 | |
| Supply current on VIO, dominant | IIO | 200 | 400 | µA | Dominant, VTXD = 0V | 13 | |
| VIO standby current | IDDS | 0.3 | 2 | µA | Bus recessive (Note 1) | 13 | |
| VIO POR high level | VPORH_VIO | 0.8 | 1.2 | 1.7 | V | 13 | |
| VIO POR low level | VPORL_VIO | 0.7 | 1.1 | 1.4 | V | 13 | |
| CANH/CANL recessive bus output voltage | VO(R) | 2 | 3 | V | VTXD = VDD, no load | 13 | |
| CANH/CANL bus output voltage in standby | VO(S) | -0.1 | 0 | 0.1 | V | STBY = VTXD = VDD, no load | 14 |
| Recessive output current | IO(R) | -5 | 5 | mA | -24V < VCAN < +24V | 14 | |
| CANH dominant output voltage | VO(D) | 2.75 | 3.5 | 4.5 | V | TXD = 0, RL = 50 to 65 | 14 |
| CANL dominant output voltage | VO(D) | 0.5 | 1.5 | 2.25 | V | RL = 50 to 65 | 14 |
| Driver symmetry | VSYM | 0.9 | 1 | 1.1 | V | 1 MHz square wave, Recessive and Dominant states, and transition (Note 1) | 14 |
| Dominant differential output voltage | VO(DIFF)(D) | 1.5 | 2 | 3 | V | VTXD = VSS, RL = 50 to 65 (Note 1) | 14 |
| Dominant differential output voltage | VO(DIFF)(D) | 1.3 | 2 | 3.3 | V | VTXD = VSS, RL = 40 to 75 | 14 |
| Recessive differential output voltage, normal | VO(DIFF)(R) | -500 | 0 | 50 | mV | VTXD = VDD, no load, normal | 14 |
| Recessive differential output voltage, standby | VO(DIFF)(S) | -200 | 0 | 200 | mV | VTXD = VDD, no load, standby | 14 |
| CANH short-circuit output current | IO(SC) | -115 | -85 | mA | VTXD = VSS, VCANH = -3V, CANL: floating | 14 | |
| CANL short-circuit output current | IO(SC) | 75 | 115 | mA | VTXD = VSS, VCANL = +18V, CANH: floating | 14 | |
| Recessive differential input voltage, normal | VDIFF(R)(I) | -4 | 0.5 | V | Normal mode, -12V < V(CANH, CANL) < +12V (Note 3) | 14 | |
| Recessive differential input voltage, standby | VDIFF(R)(I) | -4 | 0.4 | V | Standby mode, -12V < V(CANH, CANL) < +12V (Note 3) | 14 | |
| Dominant differential input voltage, normal | VDIFF(D)(I) | 0.9 | 9 | V | Normal mode, -12V < V(CANH, CANL) < +12V (Note 3) | 15 | |
| Dominant differential input voltage, standby | VDIFF(D)(I) | 1.1 | 9 | V | Standby mode, -12V < V(CANH, CANL) < +12V (Note 3) | 15 | |
| Differential receiver threshold, normal | VTH(DIFF) | 0.5 | 0.7 | 0.9 | V | Normal mode, -12V < V(CANH, CANL) < +12V (Note 3) | 15 |
| Differential receiver threshold, standby | VTH(DIFF) | 0.4 | 0.7 | 0.9 | V | Standby mode, -12V < V(CANH, CANL) < +12V (Note 3) | 15 |
| Differential input hysteresis | VHYS(DIFF) | 30 | 200 | mV | Normal mode (Note 1) | 15 | |
| Differential input resistance | RDIFF | 12 | 25 | 100 | kΩ | Note 1 | 15 |
| Internal resistance matching | mR | -3 | 0 | 3 | % | VCANH = VCANL (Note 1) | 15 |
| CANH, CANL input leakage | ILI | -5 | 5 | µA | VDD = VTXD = VSTBY = 0V, VIO = 0V, VCANH = VCANL = 5 V | 15 | |
| High-level input voltage (TXD, STBY) | VIH | 0.7 | VIO | MCP2542FD and MCP2542WFD, min 0.7 VIO | 15 | ||
| Low-level input voltage (TXD, STBY) | VIL | 0.3 | VIO | MCP2542FD and MCP2542WFD, max 0.3 VIO | 15 | ||
| High-level input current | IIH | -1 | 1 | µA | 15 | ||
| TXD low-level input current | IIL(TXD) | -270 | -150 | -30 | µA | 15 | |
| STBY low-level input current | IIL(STBY) | -30 | -1 | µA | 15 | ||
| RXD low-level output voltage | VOL | 0.4 | V | IOL = 4 mA, typical 8 mA | 16 | ||
| Shutdown junction temperature | TJ(SD) | 165 | 175 | 185 | °C | -12V < V(CANH, CANL) < +12V (Note 1) | 16 |
| Shutdown temperature hysteresis | TJ(HYST) | 15 | 30 | °C | -12V < V(CANH, CANL) < +12V (Note 1) | 16 | |
| Delay TXD low to bus dominant | tTXD-BUSON | 50 | 85 | ns | Note 1 | 17 | |
| Delay TXD high to bus recessive | tTXD-BUSOFF | 40 | 85 | ns | Note 1 | 17 | |
| Delay bus dominant to RXD | tBUSON-RXD | 70 | 85 | ns | Note 1 | 17 | |
| Delay bus recessive to RXD | tBUSOFF-RXD | 110 | 145 | ns | Note 1 | 17 | |
| Propagation delay TXD to RXD | tTXD, RXD | 90 | 120 | ns | Worst case of tLOOP(R) and tLOOP(F) | 18 | |
| CAN activity filter time (standby) | tFILTER | 0.5 | 1.7 | 3.6 | µs | VDIFF(D)(I) = 1.2V to 3V | 18 |
| Delay standby to normal mode | tWAKE | 7 | 30 | µs | Negative edge on STBY | 18 | |
| Permanent dominant detect time | tPDT | 0.8 | 1.9 | 5 | ms | TXD = 0V | 18 |
| WUP time-out | tWAKE(TO) | 1 | 1.9 | 5 | ms | MCP2542WFD/4WFD (Figure 2-11) | 19 |
| Thermal resistance, 8-lead SOIC | θJA | 149.5 | °C/W | 23 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 | 32 |
CAD (KiCad official)
- Symbol:
MCP2542WFD-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp2542wfd-e-etched.step/mcp2542wfd-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp2542wfd-e.step/mcp2542wfd-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (44 pp, sha256
484a6f42b22dcf87, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).