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MCP2542FD-H

Public Made by Adom

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Microchip Tech CAN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP2542FD-H

Microchip Tech · CAN Transceivers · SOIC-8

MCP2542FD-H from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit Data Input: when low, CANH and CANL are driven dominant; when high, they are recessive unless another node drives the bus dominant, with an internal pull-up of nominal 33 kΩ to VIO on this device.
2 VSS power_in Ground supply pin.
3 VDD power_in Positive supply voltage pin that supplies the transmitter and receiver, including the wake-up receiver.
4 RXD output CMOS-compatible receiver data output that is high when the CAN bus is recessive and low when dominant, driven from VIO on this device.
5 VIO power_in Supply for the digital I/O pins (TXD, RXD, STBY) that sets their logic levels for 1.8V to 5V I/O on this device (pin is NC on the MCP2544FD/MCP2544WFDT).
6 CANL bidirectional CAN Low-level voltage I/O that drives the low side of the CAN differential bus and disconnects from the bus when the device is not powered.
7 CANH bidirectional CAN High-level voltage I/O that drives the high side of the CAN differential bus and disconnects from the bus when the device is not powered.
8 STBY input Standby mode input that selects Normal or Standby mode, with an internal MOS pull-up to VIO (typical 660 kΩ at 5V, 1.1 MΩ at 3.3V, 4.4 MΩ at 1.8V).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC voltage at TXD, RXD, STBY and VSS -0.3 V Upper limit printed as VIO + 0.3 V (not numeric) 12
DC voltage at CANH and CANL -58 58 V 12
Transient voltage on CANH and CANL (ISO-7637) -150 100 V Figure 2-5 12
Differential bus input voltage VDIFF(I) VDIFF(I) -5 10 V t = 60 days, continuous 12
Differential bus input voltage VDIFF(I) VDIFF(I) 17 V 1000 pulses, t = 0.1 ms, VCANH = +18V 12
Dominant state detection VDIFF(I) VDIFF(I) 9 V 10000 pulses, t = 1 ms 12
Storage temperature -55 150 °C 12
Operating ambient temperature -40 150 °C 12
Virtual junction temperature TVJ -40 190 °C IEC 60747-1 12
Soldering temperature of leads 300 °C 10 seconds 12
ESD protection on CANH and CANL -13 13 kV IEC 61000-4-2 12
ESD protection on CANH and CANL -8 8 kV IEC 801; Human Body Model 12
ESD protection on all other pins -4 4 kV IEC 801; Human Body Model 12
ESD protection on all pins -400 400 V IEC 801; Machine Model 12
ESD protection on all pins -750 750 V IEC 801; Charge Device Model 12
VDD supply voltage (absolute maximum) VDD 7 V 12
VIO supply voltage (absolute maximum) VIO 7 V 12
Specified temperature range (H grade) TA -40 150 C High (H) grade 23
Operating temperature range TA -40 150 C 23
Storage temperature range TA -65 155 C 23
VDD voltage range VDD 4.5 5.5 V 13
Supply current IDD 2.5 5 mA Recessive, VTXD = VDD 13
Supply current IDD 55 70 mA Dominant, VTXD = 0V 13
Standby current IDDS 4 16 µA MCP2542FD and MCP2542WFD, includes IIO 13
Maximum supply current IDDMAX 95 140 mA Fault condition: VTXD = VSS, VCANH = VCANL = -5V to +18V (Note 1) 13
High level of the POR comparator for VDD VPORH 3 3.95 V Note 1 13
Low level of the POR comparator for VDD VPORL 1 2 3.2 V Note 1 13
High level of the UV comparator for VDD VUVH 4 4.25 4.4 V 13
Low level of the UV comparator for VDD VUVL 3.6 3.8 4 V 13
Digital supply voltage range VIO 1.7 5.5 V 13
Supply current on VIO IIO 7 20 µA Recessive, VTXD = VIO 13
CANH; CANL: Recessive bus output voltage VO(R) 2 3 V VTXD = VDD, no load 13
CANH; CANL: Bus output voltage in standby VO(S) -0.1 0 0.1 V STBY = VTXD = VDD, no load 14
CANH: Dominant output voltage VO(D) 2.75 3.5 4.5 V TXD = 0, RL = 50 to 65 14
CANL: Dominant output voltage VO(D) 0.5 1.5 2.25 V RL = 50 to 65 14
Dominant: differential output voltage VO(DIFF)(D) 1.5 2 3 V VTXD = VSS, RL = 50 to 65 14
Recessive: differential output voltage (normal) VO(DIFF)(R) -500 0 50 mV VTXD = VDD, no load, normal 14
Recessive: differential output voltage (standby) VO(DIFF)(S) -200 0 200 mV VTXD = VDD, no load, standby 14
CANH: Short-circuit output current IO(SC) -115 -85 mA VTXD = VSS, VCANH = -3V, CANL floating 14
Recessive differential input voltage (normal) VDIFF(R)(I) -4 0.5 V Normal mode, -12V < V(CANH, CANL) < +12V 14
Dominant differential input voltage (normal) VDIFF(D)(I) 0.9 9 V Normal mode, -12V < V(CANH, CANL) < +12V 15
Differential receiver threshold (normal) VTH(DIFF) 0.5 0.7 0.9 V Normal mode, -12V < V(CANH, CANL) < +12V 15
Differential input hysteresis VHYS(DIFF) 30 200 mV Normal mode, see Figure 2-6 15
TXD low-level input current IIL(TXD) -270 -150 -30 µA 15
Shutdown junction temperature TJ(SD) 165 175 185 °C -12V < V(CANH, CANL) < +12V (Note 1) 16
Shutdown temperature hysteresis TJ(HYST) 15 30 °C -12V < V(CANH, CANL) < +12V (Note 1) 16
Delay TXD low to bus dominant tTXD-BUSON 50 85 ns Note 1 17
Delay TXD high to bus recessive tTXD-BUSOFF 40 85 ns Note 1 17
Delay bus dominant to RXD tBUSON-RXD 70 85 ns Note 1 17
Delay bus recessive to RXD tBUSOFF-RXD 110 145 ns Note 1 17
Propagation delay TXD to RXD tTXD, RXD 90 120 ns Worst case of tLOOP(R) and tLOOP(F); see Figure 2-10 18
Propagation delay, rising edge tLOOP(R) 90 120 ns 18
Propagation delay, falling edge tLOOP(F) 80 120 ns 18
Recessive bit time on RXD, 2 Mbps tBIT(RXD), 2M 450 490 550 ns tBIT(TXD) = 500 ns (Figure 2-10) 18
Transmitted bit time on bus, 2 Mbps tBIT(BUS), 2M 435 515 530 ns tBIT(TXD) = 500 ns (Figure 2-10) 19
Receiver timing symmetry, 2 Mbps tDIFF(REC), 2M -65 0 40 ns tBIT(TXD) = 500 ns (Figure 2-10) 19
CAN activity filter time (standby) tFILTER 0.5 1.7 3.6 µs VDIFF(D)(I) = 1.2V to 3V 18
Delay standby to normal mode tWAKE 7 30 µs Negative edge on STBY 18
Permanent dominant detect time tPDT 0.8 1.9 5 ms TXD = 0V 18
Thermal resistance, 8-Lead SOIC JA 149.5 C/W 23

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 32

CAD (KiCad official)

  • Symbol: MCP2542FD-H
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mcp2542fd-h-etched.step / mcp2542fd-h-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp2542fd-h.step / mcp2542fd-h.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (44 pp, sha256 484a6f42b22dcf87, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF