component
MCP23S08-E
Public Made by Adomby adom
Microchip Tech I/O Expanders, SOIC-18-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MCP23S08-E
Microchip Tech · I/O Expanders · SOIC-18-300mil
MCP23S08-E from Microchip Tech, in a SOIC-18-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCK | input | SPI serial clock input (the table lists it as SCL/SCK, and the MCP23S08 uses the SCK function), with SPI rated to 10 MHz at 2.7 V to 5.5 V and 5 MHz at 1.8 V. |
| 2 | SI | input | Serial data input for the MCP23S08 SPI interface (listed as SDA/SI in the table). |
| 3 | SO | output | Serial data output for the MCP23S08 SPI interface; this pin is not a hardware address input on the S08 variant. |
| 4 | A1 | input | Hardware address input that must be biased externally. |
| 5 | A0 | input | Hardware address input that must be biased externally. |
| 6 | RESET | input | External reset input that must be biased externally. |
| 7 | CS | input | External chip select input for the MCP23S08 SPI interface (listed as NC/CS in the table). |
| 8 | INT | output | Interrupt output that can be configured as active-high, active-low or open-drain. |
| 9 | VSS | power_in | Ground reference for the device. |
| 10 | GP0 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 11 | GP1 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 12 | GP2 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 13 | GP3 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 14 | GP4 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 15 | GP5 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 16 | GP6 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 17 | GP7 | bidirectional | Bidirectional I/O pin that defaults to input and can be enabled for interrupt-on-change and/or an internal weak pull-up resistor. |
| 18 | VDD | power_in | Power supply pin; the device operates from 1.8 V to 5.5 V depending on temperature and interface speed. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-18-300mil |
| Category | Interface |
| Pins | 18 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | -40 | 125 | °C | 23 | |||
| Storage temperature | -65 | 150 | °C | 23 | |||
| Voltage on VDD with respect to VSS | -0.3 | 5.5 | V | 23 | |||
| Voltage on all other pins with respect to VSS (except VDD) | -0.6 | V | 23 | ||||
| Maximum current out of VSS pin | 150 | mA | 23 | ||||
| Maximum current into VDD pin | 125 | mA | 23 | ||||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VDD | 23 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VDD | 23 | |
| Operating ambient temperature (I-Temp) | TA | -40 | 85 | °C | 1.8V ≤ VDD ≤ 5.5V | 24 | |
| Operating ambient temperature (E-Temp) | TA | -40 | 125 | °C | 4.5V ≤ VDD ≤ 5.5V | 24 | |
| Supply Voltage | VDD | 1.8 | 5.5 | V | 24 | ||
| VDD Rise Rate to Ensure Power-on Reset | SVDD | 0.05 | V/ms | Design guidance only. Not tested. | 24 | ||
| Supply Current | IDD | 1 | mA | SCL/SCK = 1 MHz | 24 | ||
| Standby current | IDDS | 1 | µA | 24 | |||
| Standby current | 2 | µA | 4.5V - 5.5V @ +125°C (Note 1) | 24 | |||
| Input Leakage Current, I/O port pins | IIL | -1 | 1 | µA | VSS ≤ VPIN ≤ VDD | 24 | |
| Output Leakage Current, I/O port pins | ILO | -1 | 1 | µA | VSS ≤ VPIN ≤ VDD | 24 | |
| GPIO weak pull-up current | IPU | 40 | 75 | 115 | µA | VDD = 5V, GP Pins = VSS; -40°C ≤ TA ≤ +85°C | 24 |
| Output Low-Voltage, GPIO | VOL | 0.6 | V | IOL = 8.5 mA, VDD = 4.5V | 24 | ||
| Output Low-Voltage, INT | VOL | 0.6 | V | IOL = 1.6 mA, VDD = 4.5V | 24 | ||
| Output Low-Voltage, SO | VOL | 0.6 | V | IOL = 3.0 mA, VDD = 1.8V | 24 | ||
| Capacitive loading, output pins (GPIO, SO, INT) | CIO | 50 | pF | 24 | |||
| RESET Pulse Width (Low) | TRSTL | 1 | µs | 26 | |||
| Output High-Impedance From RESET Low | TIOZ | 1 | µs | 26 | |||
| Clock Frequency | FCLK | 5 | MHz | 1.8V, 5.5V (I-Temp) | 29 | ||
| Clock Frequency | FCLK | 10 | MHz | 2.7V, 5.5V (I-Temp) | 29 | ||
| CS Setup Time | TCSS | 50 | ns | 29 | |||
| CS Hold Time | TCSH | 100 | ns | 1.8V, 5.5V (I-Temp) | 29 | ||
| CS Hold Time | TCSH | 50 | ns | 2.7V, 5.5V (I-Temp) | 29 | ||
| CS Disable Time | TCSD | 100 | ns | 1.8V, 5.5V (I-Temp) | 29 | ||
| CS Disable Time | TCSD | 50 | ns | 2.7V, 5.5V (I-Temp) | 29 | ||
| Data Setup Time | TSU | 20 | ns | 1.8V, 5.5V (I-Temp) | 29 | ||
| Data Setup Time | TSU | 10 | ns | 2.7V, 5.5V (I-Temp) | 29 | ||
| Data Hold Time | THD | 20 | ns | 1.8V, 5.5V (I-Temp) | 29 | ||
| Data Hold Time | THD | 10 | ns | 2.7V, 5.5V (I-Temp) | 29 | ||
| CLK Rise Time | TR | 2 | µs | Note 1 | 29 | ||
| CLK Fall Time | TF | 2 | µs | Note 1 | 29 | ||
| Clock High Time | THI | 90 | ns | 1.8V, 5.5V (I-Temp) | 29 | ||
| Clock High Time | THI | 45 | ns | 2.7V, 5.5V (I-Temp) | 29 | ||
| Clock Low Time | TLO | 90 | ns | 1.8V, 5.5V (I-Temp) | 30 | ||
| Clock Low Time | TLO | 45 | ns | 2.7V, 5.5V (I-Temp) | 30 | ||
| Output Valid from Clock Low | TV | 90 | ns | 1.8V, 5.5V (I-Temp) | 30 | ||
| Output Valid from Clock Low | TV | 45 | ns | 2.7V, 5.5V (I-Temp) | 30 | ||
| Output Hold Time | THO | 0 | ns | 30 | |||
| Output Disable Time | TDIS | 100 | ns | 30 | |||
| Serial data to output valid | TGPOV | 500 | ns | 31 | |||
| Interrupt pin disable time | TINTD | 600 | ns | 31 | |||
| GP input change to register valid | TGPIV | 450 | ns | 31 | |||
| IOC event to INT active | TGPINT | 600 | ns | 31 | |||
| Glitch Filter on GP Pins | TGLITCH | 150 | ns | 31 |
CAD (KiCad official)
- Symbol:
MCP23S08-E - Footprint:
Package_SO:SOIC-18W_7.5x11.6mm_P1.27mm - 3D model: SOIC-18-300mil (KiCad packages3D, STEP)
- 3D model files:
mcp23s08-e-etched.step/mcp23s08-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp23s08-e.step/mcp23s08-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (44 pp, sha256
573ae3991f57d129, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).