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MCP2221A-I

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Microchip Tech USB Converters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MCP2221A-I

Microchip Tech · USB Converters · TSSOP-14

MCP2221A-I from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply pin with an operating voltage of 3.0 to 5.5V, and its level sets the logic-high voltage on the GPIO and UART TX/RX pins.
2 GP0 bidirectional General purpose I/O pin that can alternatively be configured as the SSPND output or the LED_URX UART receive activity output (factory default).
3 GP1 bidirectional General purpose I/O pin that can alternatively be configured as the CLKR clock output, ADC1 analog input, LED_UTX UART transmit activity output (factory default), or IOC external interrupt input.
4 RST input Reset input with an internal pull-up.
5 URX input UART RX pin, serving as the UART data input.
6 UTX output UART TX pin, serving as the UART data output.
7 GP2 bidirectional General purpose I/O pin that can alternatively be configured as the USBCFG output (factory default), ADC2 analog input, or DAC1 analog output.
8 GP3 bidirectional General purpose I/O pin that can alternatively be configured as the LED_I2C output, ADC3 analog input, or DAC2 analog output.
9 SDA bidirectional I2C data line.
10 SCL bidirectional I2C clock line.
11 VUSB power_in USB power pin, internally connected to 3.3V, which should be locally bypassed with a high-quality ceramic capacitor.
12 D- bidirectional USB D- data line.
13 D+ bidirectional USB D+ data line.
14 VSS power_in Ground pin.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TSSOP-14
Category Interface
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias TA -40 85 °C 57
Storage temperature TSTG -65 150 °C 57
Voltage on VDD with respect to VSS VDD -0.3 6 V 57
Voltage on RST with respect to VSS VRST -0.3 9 V 57
Voltage on VUSB pin with respect to VSS VUSB -0.3 4 V 57
Voltage on D+ and D- pins with respect to VSS VD+, VD- -0.3 V 57
Voltage on all other pins with respect to VSS -0.3 V 57
Maximum current out of VSS pin 95 mA 57
Maximum current into VDD pin 95 mA 57
Clamp current IK 20 mA VPIN < 0 or VPIN > VDD 57
Maximum current sunk by all ports 90 mA 57
Maximum current sourced by all ports 90 mA 57
Supply Voltage VDD 3 5.5 V Operating conditions 3.0V ≤ VDD ≤ 5.5V 58
Operating temperature (I-Temp) TA -40 85 °C I-Temp 58
RST pin pull-up resistor to VDD (POR) 1 10 kΩ Tie RST to VDD through a resistor 21
VUSB bypass capacitor (ceramic) 0.22 0.47 µF Ceramic capacitor on VUSB 17
Supply Rise Rate to Ensure POR SVDD 0.05 V/ms Design guidance only; Not tested 58
POR Release Voltage VPOR 1.6 V 58
Supply Current IDD 10 12 mA FOSC = 12 MHz, (330 nF on VUSB); VDD = 3.0V 58
Supply Current IDD 13 15 mA FOSC = 12 MHz, (330 nF on VUSB); VDD = 5.0V 58
Input Low-Voltage Schmitt Trigger (URX) VIL 0.2 VDD 3.0V ≤ VDD ≤ 5.5V 58
Input Low-Voltage TTL (GP pins) VIL 0.8 V 4.5V ≤ VDD ≤ 5.5V 58
Input High-Voltage Schmitt Trigger (URX) VIH 0.8 VDD 3.0V ≤ VDD ≤ 5.5V 58
Input High-Voltage TTL (GP pins) VIH 2 V 4.5V ≤ VDD ≤ 5.5V 58
Input Leakage Current GP, URX IIL -100 100 nA VSS ≤ VPIN ≤ VDD, pin at high-Z 58
Output Low-Voltage GP, UTX VOL 0.6 V IOL = 8.0 mA, VDD = 5.0V 58
Output High-Voltage GP, UTX VOH 0.7 V below VDD IOH = -3.5 mA, VDD = 5.0V 58
GPIO Capacitive Loading CIO 50 pF Note 1 58
USB Voltage VUSB 3 3.6 V Voltage on the VUSB pin must be in this range for proper USB operation 59
Input Leakage on Pin IIL -1 1 µA VSS ≤ VPIN ≤ VDD, pin at high-impedance 59
Input Low Voltage for USB Buffer VILUSB 0.8 V For VUSB range 59
Input High Voltage for USB Buffer VIHUSB 2 V For VUSB range 59
Differential Input Sensitivity VDIFS 0.2 V The difference between D+ and D- must exceed this value while VCM is met 59
Differential Common Mode Range VCM 0.8 2.5 V 59
Driver Output Impedance ZOUT 28 44 Ω 59
Voltage Output Low VOL 0 0.3 V 1.5 k load connected to 3.6V 59
Voltage Output High VOH 2.8 3.6 V 1.5 k load connected to ground 59
ADC Resolution NR 10 bit 60
Recommended Impedance of Analog Voltage Source ZAIN 10 kΩ Can go higher if external 0.01F capacitor is present on input pin. 60
Settling Time CST 10 µs Settling time measured while DACVAL<4:0> transitions from '0000' to '1111' 60
RST Pulse Width (low) TRST 2 µs 62
Power-up Timer TPWRT 40 65 140 ms 62
CLKR clock frequency tolerance -0.25 0.25 % Nominal 12 MHz clock output 21
Internal oscillator clock accuracy over temperature 2500 ppm Over temperature 21
Unit Resistor Value (R) CR 5 kΩ 60
Oscillator Start-Up Time TOST 1024 TOST 62
Standby Current IDDS 46 µA 58
POR Rearm Voltage 0.8 V 58
Thermal Resistance Junction to Ambient (14-pin TSSOP) θJA 100 C/W 14-pin TSSOP package 60
Thermal Resistance Junction to Case (14-pin TSSOP) θJC 24.4 C/W 14-pin TSSOP package 60
Maximum Junction Temperature TJMAX 150 °C 60

CAD (KiCad official)

  • Symbol: MCP2221A-I
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: mcp2221a-i-etched.step / mcp2221a-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp2221a-i.step / mcp2221a-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (80 pp, sha256 7760f2692b2469e1, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF