# MCP2210T-I

**Microchip Tech** · USB ICs · QFN-20-EP(5x5)

MCP2210T-I from Microchip Tech, in a QFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST | input | Reset input; a Reset is generated by holding the pin low, and it can be tied through 1 kΩ to 10 kΩ to VDD to use the POR circuit. |
| 2 | GP0 | bidirectional | General purpose I/O pin (GPIO0) with alternate function Chip Select CS0. |
| 3 | GP1 | bidirectional | General purpose I/O pin (GPIO1) with alternate function Chip Select CS1 (default SPI chip select line). |
| 4 | GP2 | bidirectional | General purpose I/O pin (GPIO2) with alternate function Chip Select CS2 or USB Suspend (SSPND). |
| 5 | GP3 | bidirectional | General purpose I/O pin (GPIO3) with alternate function Chip Select CS3 or SPI Transfer Traffic LED. |
| 6 | MOSI | output | SPI Host output. |
| 7 | GP4 | bidirectional | General purpose I/O pin (GPIO4) with alternate function Chip Select CS4 or USB Low Power. |
| 8 | SCK | output | SPI Clock output. |
| 9 | GP5 | bidirectional | General purpose I/O pin (GPIO5) with alternate function Chip Select CS5 or USB Configured (USBCFG). |
| 10 | MISO | input | SPI Host input. |
| 11 | GP6 | bidirectional | General purpose I/O pin (GPIO6) with alternate function Chip Select CS6 or External Interrupt. |
| 12 | GP7 | bidirectional | General purpose I/O pin (GPIO7) with alternate function Chip Select CS7 or SPI Bus Release ACK. |
| 13 | GP8 | input | Digital input only pin, with alternate function SPI Bus Release REQ. |
| 14 | VUSB | power_out | USB regulator (3.3V) output that powers the USB transceiver; needs a 0.22 to 0.47 µF ceramic bypass capacitor, or an external regulated 3.3V when VDD is low. |
| 15 | D- | bidirectional | USB D- differential data line. |
| 16 | D+ | bidirectional | USB D+ differential data line. |
| 17 | VSS | power_in | Ground. |
| 18 | VDD | power_in | Positive supply, operating voltage 3.3-5.5V, which also sets the logic levels of the GP and SPI pins. |
| 19 | OSC1 | input | Oscillator input for the 12 MHz crystal or resonator. |
| 20 | OSC2 | output | Oscillator output for the 12 MHz crystal or resonator. |
| 21 | EP | passive | Exposed thermal pad on the bottom of the QFN package. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-20-EP(5x5) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 3.3 |  | 5.5 | V |  | 62 |
| Power-on Reset Release Voltage | VPOR |  | 1.6 |  | V |  | 62 |
| Power-on Reset Rearm Voltage | VPORR |  | 0.8 |  | V |  | 62 |
| VDD Rise Rate to Ensure Power-on Reset | SVDD | 0.05 |  |  | V/ms | Design guidance only, Not tested | 62 |
| Supply Current | IDD |  | 10 | 12 | mA | VDD = 3.0V, FOSC = 12 MHz (330 nF on VUSB) | 62 |
| Supply Current | IDD |  | 13 | 15 | mA | VDD = 5.0V, FOSC = 12 MHz (330 nF on VUSB) | 62 |
| Standby current | IDDS |  | 9 |  | µA |  | 62 |
| Input Low Voltage, Schmitt Trigger (GP0-3, 6-8, MOSI, MISO, SCK) | VIL |  |  | 0.2 | V | 3.0V ≤ VDD ≤ 5.5V; max is 0.2 VDD | 62 |
| Input Low Voltage, TTL (GP4, GP5) | VIL |  |  | 0.8 | V | 4.5V ≤ VDD ≤ 5.5V | 62 |
| Input High Voltage, Schmitt Trigger (GP0-3, 6-8, MOSI, MISO, SCK) | VIH | 0.8 |  |  | V | 3.0V ≤ VDD ≤ 5.5V; min is 0.8 VDD, max VDD | 62 |
| Input High Voltage, TTL (GP4, GP5) | VIH | 2 |  |  | V | 4.5V ≤ VDD ≤ 5.5V; max VDD | 62 |
| Input Leakage Current GP0-8, MOSI, MISO, SCK | IIL | -100 | 50 | 100 | nA | VSS ≤ VPIN ≤ VDD, pin at Hi-Z | 62 |
| Input Leakage Current RST | IIL | -200 | 50 | 200 | nA | VSS ≤ VPIN ≤ VDD, pin at Hi-Z | 62 |
| Input Leakage Current OSC1 | IIL | -100 | 50 | 100 | nA | VSS ≤ VPIN ≤ VDD, pin at Hi-Z | 62 |
| Output Low Voltage GP0-7, MOSI, MISO, SCK | VOL |  |  | 0.6 | V | IOL = 8.0 mA, VDD = 5.0V | 62 |
| Output High Voltage GP0-7, MOSI, MISO, SCK | VOH | -0.7 |  |  | V | IOH = -3.5 mA, VDD = 5.0V; min is VDD, 0.7 | 62 |
| OSC2 Capacitive Loading | COSC2 |  |  | 15 | pF | Note 1 | 62 |
| GP0-7, MOSI, MISO, SCK Capacitive Loading | CIO |  |  | 50 | pF | Note 1 | 62 |
| USB Voltage | VUSB | 3 |  | 3.6 | V | Voltage on VUSB pin must be in this range for proper USB operation | 63 |
| USB Input Leakage on Pin | IIL | -1 |  | 1 | µA | VSS ≤ VPIN ≤ VDD pin at high-impedance | 63 |
| Input Low Voltage for USB Buffer | VILUSB |  |  | 0.8 | V | For VUSB range | 63 |
| Input High Voltage for USB Buffer | VIHUSB | 2 |  |  | V | For VUSB range | 63 |
| Differential Input Sensitivity | VDIFS |  |  | 0.2 | V | Difference between D+ and D- must exceed this value while VCM is met | 63 |
| Differential Common Mode Range | VCM | 0.8 |  | 2.5 | V |  | 63 |
| Driver Output Impedance | ZOUT | 28 |  | 44 | Ω |  | 63 |
| USB Voltage Output Low | VOL | 0 |  | 0.3 | V | 1.5 kΩ load connected to 3.6V | 63 |
| USB Voltage Output High | VOH | 2.8 |  | 3.6 | V | 1.5 kΩ load connected to ground | 63 |
| MCLR Pulse Width (low) | TRST | 2 |  |  | µs |  | 66 |
| Power-up timer | TPWRT | 40 | 65 | 140 | ms |  | 66 |
| Oscillator start-up time | TOST |  | 1024 |  | TOST |  | 66 |
| Voltage on VDD with respect to VSS | VDD | -0.3 |  | 6 | V |  | 61 |
| Voltage on MCLR with respect to Vss | MCLR | -0.3 |  | 9 | V |  | 61 |
| Voltage on VUSB pin with respect to VSS | VUSB | -0.3 |  | 4 | V | VUSB must always be ≤ VDD + 0.3V | 61 |
| Voltage on D+ and D- pins with respect to VSS |  | -0.3 |  |  | V | max is VUSB + 0.3V | 61 |
| Voltage on all other pins with respect to VSS |  | -0.3 |  |  | V | max is VDD + 0.3V | 61 |
| Ambient temperature under bias |  | -40 |  | 85 | °C |  | 61 |
| Storage temperature |  | -65 |  | 150 | °C |  | 61 |
| Maximum current out of VSS pin |  |  |  | 95 | mA |  | 61 |
| Maximum current into VDD pin |  |  |  | 95 | mA |  | 61 |
| Clamp current | IK |  |  | 20 | mA | VPIN < 0 or VPIN > VDD | 61 |
| Maximum output current sunk by any I/O pin |  |  |  | 25 | mA |  | 61 |
| Maximum output current sourced by any I/O pin |  |  |  | 25 | mA |  | 61 |
| Maximum current sunk by all ports |  |  |  | 90 | mA |  | 61 |
| Maximum current sourced by all ports |  |  |  | 90 | mA |  | 61 |
| Operating temperature | TA | -40 |  | 85 | °C | I-Temp | 64 |
| Thermal Resistance Junction to Ambient | θJA |  | 36.1 |  | °C/W | 20-pin QFN 5x5 mm package | 64 |
| Thermal Resistance Junction to Case | θJC |  | 1.7 |  | °C/W | 20-pin QFN 5x5 mm package | 64 |
| Maximum Junction Temperature | TJMAX |  | 150 |  | °C |  | 64 |
| Oscillator input frequency |  |  | 12 |  | MHz | clock input accuracy ±0.25% (2,500 ppm maximum) | 8 |

## CAD (KiCad official)

- Symbol: `MCP2210T-I`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm`
- 3D model: QFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `mcp2210t-i-etched.step` / `mcp2210t-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp2210t-i.step` / `mcp2210t-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp2210t-i-datasheet.pdf) (82 pp, sha256 `7d13cb9771145e07`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp2210t-i-datasheet.pdf)