component
MCP2122T-E
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Microchip Tech Interface - Specialized, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP2122T-E
Microchip Tech · Interface - Specialized · SOIC-8
MCP2122T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 16XCLK | input | 16x external clock source input that sets the baud rate of the host UART and IR interfaces. |
| 2 | TX | input | Asynchronous receive input from the Host Controller UART, Schmitt trigger input with CMOS levels. |
| 3 | RX | output | Asynchronous transmit output to the Host Controller UART. |
| 4 | VSS | power_in | Ground reference for logic and I/O pins. |
| 5 | RESET | input | Resets the device when low; high (H) is normal operation and low (L) holds the device in reset. |
| 6 | RXIR | input | Asynchronous receive input from the infrared transceiver, Schmitt trigger input with CMOS levels. |
| 7 | TXIR | output | Asynchronous transmit output to the infrared transceiver. |
| 8 | VDD | power_in | Positive supply for logic and I/O pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 1.8 | 5.5 | V | See Figure 4-1 | 17 | |
| Operating Temperature (extended) | TA | -40 | 125 | °C | Standard Operating Conditions, extended | 17 | |
| Ambient Temperature under bias | -40 | 125 | °C | 15 | |||
| Storage Temperature | -65 | 150 | °C | 15 | |||
| Voltage on VDD with respect to VSS | VDD | -0.3 | 6.5 | V | 15 | ||
| Voltage on RESET with respect to VSS | RESET | -0.3 | 14 | V | 15 | ||
| Voltage on all other pins with respect to VSS | -0.3 | V | Max is VDD + 0.3V | 15 | |||
| Input Clamp Current | IIK | -20 | 20 | mA | VI < 0 or VI > VDD | 15 | |
| Output Clamp Current | IOK | -20 | 20 | mA | V0 < 0 or V0 > VDD | 15 | |
| Supply Current | IDD | 0.1 | 1 | mA | FOSC = 1.8432 MHz, VDD = 5.5V (TX = H, RXIR = H) | 17 | |
| Supply Current Transmitter | IDD | 300 | µA | Transmitter (TX = L, RXIR = H); FOSC = 1.8432 MHz, VDD = 1.8V | 17 | ||
| Supply Current Transmitter | IDD | 1 | mA | Transmitter (TX = L, RXIR = H); FOSC = 1.8432 MHz, VDD = 5.5V | 17 | ||
| Supply Current Receiver | IDD | 500 | µA | Receiver (RXIR = L, TX = H); FOSC = 1.8432 MHz, VDD = 1.8V | 17 | ||
| Supply Current Receiver | IDD | 2 | mA | Receiver (RXIR = L, TX = H); FOSC = 1.8432 MHz, VDD = 5.5V | 17 | ||
| Device Disabled Current | IPD | 2 | µA | VDD = 1.8V | 17 | ||
| Device Disabled Current | IPD | 4 | µA | VDD = 5.5V | 17 | ||
| Output Low-Voltage RX | VOL | 0.6 | V | IOL = 2 mA, VDD = 1.8V | 19 | ||
| Output Low-Voltage TXIR | VOL | 0.6 | V | IOL = 2 mA, VDD = 1.8V | 19 | ||
| Capacitive Loading on All Output pins | COUT | 50 | pF | All Output pins | 19 | ||
| External 16XCLK Period | 1TXCLK | 542.5 | ns | 21 | |||
| External 16XCLK Frequency | 1A FXCLK | 1.8432 | MHz | External 16XCLK frequency | 21 | ||
| Clock Error | 1C EXCLK | -2 | 2 | % | Note 5 | 21 | |
| Clock in (16XCLK) Low or High Time | 3 TXCLKL, TXCLKH | 50 | ns | Clock in (16XCLK) low or high time | 21 | ||
| Clock in (16XCLK) Rise or Fall Time | 4 TXCLKR, TXCLKF | 7.5 | ns | Note 5 | 21 | ||
| RX pin rise time | 20A ToR | 10 | 25 | ns | VDD ≥ 2.7V (Note 3) | 22 | |
| RX pin rise time | 20B | 10 | 60 | ns | VDD = 1.8V (Note 3) | 22 | |
| TXIR pin rise time | 20C | 10 | 25 | ns | VDD ≥ 2.7V (Note 3) | 22 | |
| TXIR pin rise time | 20D | 10 | 60 | ns | VDD = 1.8V (Note 3) | 22 | |
| RX pin fall time | 21A ToF | 10 | 35 | ns | Note 3 | 22 | |
| TXIR pin fall time | 21C | 10 | 25 | ns | Note 3 | 22 | |
| RESET Pulse Width (low) | 30 TRSTL | 2000 | ns | VDD = 5.0 V | 23 | ||
| Default output state of TXIR pin from RESET Low | 34A ToD | 2 | µs | 23 | |||
| Default output state of RX pins from RESET Low | 34B ToD | 2 | µs | 23 | |||
| Transmit Baud Rate (TXIR) | IR100B TTXIRBIT | 16 | 16 | TXCLK | 24 | ||
| TX pin rise time and fall time | IR113 TTXRF | 25 | ns | Note 2 | 24 | ||
| 16XCLK to TX jitter | IR114 TTXPDIRJ | 1 | TXCLK | Note 2 | 24 | ||
| TX falling edge to TXIR rising edge | IR120 TTXL2TXIRH | 7 | 8 | TXCLK | Note 1 | 24 | |
| TXIR pulse width | IR121A TTXIRPW | 3 | 3 | TXCLK | At 115200 baud | 24 | |
| TXIR pulse width | IR121B TTXIRPW | 1.41 | 3.5 | 5 | µs | At 9600 baud (Note 5) | 24 |
| TXIR pin rise and fall time | IR123 TTXIRRF | 10 | ns | 50 pF load (Note 2) | 24 | ||
| RX pin rise time and fall time | IR103 TTXRF | 25 | ns | 26 | |||
| Receive (RX pin) Bit Rate | IR110 TRXBIT | 16 | 16 | TXCLK | 26 | ||
| 16XCLK to RXIR jitter | IR133 TRXIRJ | 1 | TXCLK | Note 2 | 26 | ||
| 16XCLK to RX skew | IR134 TRXSKW | 2.5 | µs | 26 | |||
| RXIR Filter | IR135 TRXPDFIL | 0.7 | 1.4 | µs | Note 5 | 26 | |
| Host UART TX Error | IR102A ETXBIT | -2 | 2 | % | Note 2, 3 | 24 | |
| RXIR Error | IR101A ERXIRBIT | -2 | 2 | % | Note 2, 3 | 26 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN or OA), Narrow, 3.90 mm Body [SOIC] Notes: | 31 |
CAD (KiCad official)
- Symbol:
MCP2122T-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp2122t-e-etched.step/mcp2122t-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp2122t-e.step/mcp2122t-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (38 pp, sha256
912404fa52a5b8ef, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP2122T-E
**Microchip Tech** · Interface - Specialized · SOIC-8
MCP2122T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 16XCLK | input | 16x external clock source input that sets the baud rate of the host UART and IR interfaces. |
| 2 | TX | input | Asynchronous receive input from the Host Controller UART, Schmitt trigger input with CMOS levels. |
| 3 | RX | output | Asynchronous transmit output to the Host Controller UART. |
| 4 | VSS | power_in | Ground reference for logic and I/O pins. |
| 5 | RESET | input | Resets the device when low; high (H) is normal operation and low (L) holds the device in reset. |
| 6 | RXIR | input | Asynchronous receive input from the infrared transceiver, Schmitt trigger input with CMOS levels. |
| 7 | TXIR | output | Asynchronous transmit output to the infrared transceiver. |
| 8 | VDD | power_in | Positive supply for logic and I/O pins. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 1.8 | | 5.5 | V | See Figure 4-1 | 17 |
| Operating Temperature (extended) | TA | -40 | | 125 | °C | Standard Operating Conditions, extended | 17 |
| Ambient Temperature under bias | | -40 | | 125 | °C | | 15 |
| Storage Temperature | | -65 | | 150 | °C | | 15 |
| Voltage on VDD with respect to VSS | VDD | -0.3 | | 6.5 | V | | 15 |
| Voltage on RESET with respect to VSS | RESET | -0.3 | | 14 | V | | 15 |
| Voltage on all other pins with respect to VSS | | -0.3 | | | V | Max is VDD + 0.3V | 15 |
| Input Clamp Current | IIK | -20 | | 20 | mA | VI < 0 or VI > VDD | 15 |
| Output Clamp Current | IOK | -20 | | 20 | mA | V0 < 0 or V0 > VDD | 15 |
| Supply Current | IDD | | 0.1 | 1 | mA | FOSC = 1.8432 MHz, VDD = 5.5V (TX = H, RXIR = H) | 17 |
| Supply Current Transmitter | IDD | | | 300 | µA | Transmitter (TX = L, RXIR = H); FOSC = 1.8432 MHz, VDD = 1.8V | 17 |
| Supply Current Transmitter | IDD | | | 1 | mA | Transmitter (TX = L, RXIR = H); FOSC = 1.8432 MHz, VDD = 5.5V | 17 |
| Supply Current Receiver | IDD | | | 500 | µA | Receiver (RXIR = L, TX = H); FOSC = 1.8432 MHz, VDD = 1.8V | 17 |
| Supply Current Receiver | IDD | | | 2 | mA | Receiver (RXIR = L, TX = H); FOSC = 1.8432 MHz, VDD = 5.5V | 17 |
| Device Disabled Current | IPD | | | 2 | µA | VDD = 1.8V | 17 |
| Device Disabled Current | IPD | | | 4 | µA | VDD = 5.5V | 17 |
| Output Low-Voltage RX | VOL | | | 0.6 | V | IOL = 2 mA, VDD = 1.8V | 19 |
| Output Low-Voltage TXIR | VOL | | | 0.6 | V | IOL = 2 mA, VDD = 1.8V | 19 |
| Capacitive Loading on All Output pins | COUT | | | 50 | pF | All Output pins | 19 |
| External 16XCLK Period | 1TXCLK | 542.5 | | | ns | | 21 |
| External 16XCLK Frequency | 1A FXCLK | | | 1.8432 | MHz | External 16XCLK frequency | 21 |
| Clock Error | 1C EXCLK | -2 | | 2 | % | Note 5 | 21 |
| Clock in (16XCLK) Low or High Time | 3 TXCLKL, TXCLKH | 50 | | | ns | Clock in (16XCLK) low or high time | 21 |
| Clock in (16XCLK) Rise or Fall Time | 4 TXCLKR, TXCLKF | | | 7.5 | ns | Note 5 | 21 |
| RX pin rise time | 20A ToR | | 10 | 25 | ns | VDD ≥ 2.7V (Note 3) | 22 |
| RX pin rise time | 20B | | 10 | 60 | ns | VDD = 1.8V (Note 3) | 22 |
| TXIR pin rise time | 20C | | 10 | 25 | ns | VDD ≥ 2.7V (Note 3) | 22 |
| TXIR pin rise time | 20D | | 10 | 60 | ns | VDD = 1.8V (Note 3) | 22 |
| RX pin fall time | 21A ToF | | 10 | 35 | ns | Note 3 | 22 |
| TXIR pin fall time | 21C | | 10 | 25 | ns | Note 3 | 22 |
| RESET Pulse Width (low) | 30 TRSTL | 2000 | | | ns | VDD = 5.0 V | 23 |
| Default output state of TXIR pin from RESET Low | 34A ToD | | | 2 | µs | | 23 |
| Default output state of RX pins from RESET Low | 34B ToD | | | 2 | µs | | 23 |
| Transmit Baud Rate (TXIR) | IR100B TTXIRBIT | 16 | | 16 | TXCLK | | 24 |
| TX pin rise time and fall time | IR113 TTXRF | | | 25 | ns | Note 2 | 24 |
| 16XCLK to TX jitter | IR114 TTXPDIRJ | | | 1 | TXCLK | Note 2 | 24 |
| TX falling edge to TXIR rising edge | IR120 TTXL2TXIRH | 7 | | 8 | TXCLK | Note 1 | 24 |
| TXIR pulse width | IR121A TTXIRPW | 3 | | 3 | TXCLK | At 115200 baud | 24 |
| TXIR pulse width | IR121B TTXIRPW | 1.41 | 3.5 | 5 | µs | At 9600 baud (Note 5) | 24 |
| TXIR pin rise and fall time | IR123 TTXIRRF | | | 10 | ns | 50 pF load (Note 2) | 24 |
| RX pin rise time and fall time | IR103 TTXRF | | | 25 | ns | | 26 |
| Receive (RX pin) Bit Rate | IR110 TRXBIT | 16 | | 16 | TXCLK | | 26 |
| 16XCLK to RXIR jitter | IR133 TRXIRJ | | | 1 | TXCLK | Note 2 | 26 |
| 16XCLK to RX skew | IR134 TRXSKW | | | 2.5 | µs | | 26 |
| RXIR Filter | IR135 TRXPDFIL | 0.7 | | 1.4 | µs | Note 5 | 26 |
| Host UART TX Error | IR102A ETXBIT | -2 | | 2 | % | Note 2, 3 | 24 |
| RXIR Error | IR101A ERXIRBIT | -2 | | 2 | % | Note 2, 3 | 26 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | 8-Lead Plastic Small Outline (SN or OA), Narrow, 3.90 mm Body [SOIC] Notes: | 31 |
## CAD (KiCad official)
- Symbol: `MCP2122T-E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mcp2122t-e-etched.step` / `mcp2122t-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp2122t-e.step` / `mcp2122t-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/21894c.pdf) (38 pp, sha256 `912404fa52a5b8ef`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp2122t-e-datasheet.pdf)