component
MCP2003BT-H
Public Made by Adomby adom
Microchip Tech LIN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownMCP2003BT-H
Microchip Tech · LIN Transceivers · SOIC-8
MCP2003BT-H from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RXD | output | Open-drain receive data output that follows the LIN pin state except in Power-Down mode, is high-voltage tolerant, and must be connected to a valid supply through a pull-up resistor. |
| 2 | CS | input | Chip select TTL input, high-voltage tolerant, with an internal pull-down to ground that must detect a high level to activate the transmitter and should not be tied high. |
| 3 | WAKE | input | High-voltage tolerant wake-up input with an internal 800 kΩ pull-up to VBB, where a falling edge wakes the device from Power-Down mode into Ready mode. |
| 4 | TXD | input | High-voltage tolerant TTL transmit data input with an internal pull-up that drives LIN dominant when low and recessive when high, and is forced to 1 whenever the transmitter is disabled. |
| 5 | VSS | power_in | Ground pin for the device; loss of ground causes the LIN pin to become high impedance. |
| 6 | LBUS | bidirectional | Bidirectional LIN bus pin controlled by TXD with a current-limited open-collector output (short-circuit current limit 50 to 200 mA) and an internal LIN receiver. |
| 7 | VBB | power_in | Battery positive supply pin, rated for 5.5 V to 30.0 V continuous operation, and requires external reverse-battery and load-dump protection as described in the application notes. |
| 8 | VREN | output | Open-drain voltage regulator enable output that is pulled high to VBB in all modes except Power-Down and is used to drive an external regulator enable input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Battery supply voltage VBB (continuous operating range) | VBB | 5.5 | 30 | V | All limits specified for VBB = 5.5V to 30.0V | 10 | |
| Ambient temperature, High (H) range | TA | -40 | 150 | °C | High (H) temperature range | 10 | |
| Battery Voltage, continuous, non-operating | VBB | -0.3 | 50 | V | Continuous, non-operating (Note 1) | 9 | |
| Battery Voltage, non-operating (LIN bus recessive) | VBB | -0.3 | 60 | V | Non-operating, LIN bus recessive (Note 2) | 9 | |
| Bus Voltage, continuous | VLBUS | -18 | 50 | V | Continuous | 9 | |
| Maximum Junction Temperature | 150 | C | 9 | ||||
| VBB Quiescent Operating Current | IBBQ | 65 | 150 | µA | Operating Mode, bus recessive | 10 | |
| VBB Quiescent Operating Current | IBBQ | 160 | µA | VBB > 18V | 10 | ||
| VBB Transmitter-off Current | IBBTO | 60 | 120 | µA | Transmitter off, bus recessive | 10 | |
| VBB Transmitter-off Current | IBBTO | 130 | µA | VBB > 18V | 10 | ||
| VBB Power-Down Current | IBBPD | 6 | 15 | µA | 10 | ||
| VBB Power-Down Current | IBBPD | 20 | µA | VBB > 18V | 10 | ||
| VBB Power-Down Current (LIN bus shorted to GND) | IBBPD | 14 | 20 | µA | LIN bus shorted to GND; VLIN = 0V, VBB < 12V | 10 | |
| VBB Current with VSS Floating | IBBNOGND | -1 | 1 | mA | VBB = 12V, GND to VBB, VLIN = 0-27V | 10 | |
| VBB Undervoltage Threshold (switching from Operation mode to TOFF and VREN OFF) | VBBUV_FALL | 3.8 | 4 | 4.4 | V | VBB falling (Note 3) | 10 |
| VBB Undervoltage Recovery Threshold (switching from POR to Ready mode) | VBBUV_RISE | 5.5 | 5.6 | 6 | V | VBB rising (Note 3) | 10 |
| High-Level Input Voltage (TXD) | VIH | 2 | 30 | V | 10 | ||
| Low-Level Input Voltage (TXD) | VIL | -0.3 | 0.8 | V | 10 | ||
| High-Level Input Current (TXD) | IIH | -5 | µA | Input voltage = 4.0V | 10 | ||
| Low-Level Input Current (TXD) | IIL | -12 | µA | Input voltage = 0.5V | 11 | ||
| High-Level Voltage (VREN) | VHVREN | -0.3 | V | 11 | |||
| High-Level Output Current (VREN) | IHVREN | -40 | -5 | mA | Output voltage = VBB - 0.5V | 11 | |
| High-Level Output Current (VREN) | IHVREN | -120 | -20 | mA | Output voltage = VBB - 2.0V | 11 | |
| High-Level Input Voltage (CS) | VIH | 2 | 30 | V | Through a current limiting resistor | 11 | |
| Low-Level Input Voltage (CS) | VIL | -0.3 | 0.8 | V | 11 | ||
| High-Level Input Current (CS) | IIH | 10 | µA | Input voltage = 4.0V | 11 | ||
| Low-Level Input Current (CS) | IIL | 7 | µA | Input voltage = 0.5V | 11 | ||
| High-Level Input Current (WAKE) | IIH | -12 | µA | 11 | |||
| High-Level Input Current (WAKE) | IIH | -15 | µA | VBB > 18V | 11 | ||
| Low-Level Input Current (WAKE) | IIL | -30 | µA | 11 | |||
| Low-Level Input Current (WAKE) | IIL | -45 | µA | VBB > 18V | 11 | ||
| Low-Level Output Voltage (RXD) | VOL | 0.4 | V | IIN = 2 mA | 11 | ||
| High-Level Output Current (RXD) | IOH | -1 | -1 | µA | VLIN = VBB, VRXD = 5.5V | 11 | |
| Low-Level Input Voltage (LBUS), dominant state | VIL(LBUS) | -8 | V | Dominant state | 11 | ||
| Low-Level Output Current (LBUS) | IOL(LBUS) | 40 | 200 | mA | Output voltage = 0.2 VBB, VBB = 12V | 11 | |
| Low-Level Output Current (LBUS) | IOL(LBUS) | 16.5 | mA | Output voltage = 0.2 VBB, VBB = 18V | 11 | ||
| High-Level Output Current (LBUS) | IOH(LBUS) | 20 | µA | 11 | |||
| Short-Circuit Current Limit | ISC | 50 | 200 | mA | Note 1 | 11 | |
| Driver Dominant Voltage | V_LOSUP | 1.2 | V | RLOAD = 500 | 11 | ||
| Input Leakage Current (at the receiver during dominant bus level) | IBUS_PAS_DOM | -1 | -0.4 | mA | Driver off, VBUS = 0V, VBB = 12V | 11 | |
| Input Leakage Current (at the receiver during recessive bus level) | IBUS_PAS_REC | 12 | 20 | µA | Driver off, 8V < VBB < 18V, 8V < VBUS < 18V | 12 | |
| Leakage Current (disconnected from ground) | IBUS_NO_GND | -10 | 1 | 10 | µA | GNDDEVICE = VBB, 0V < VBUS < 18V, VBB = 12V | 12 |
| Leakage Current (disconnected from VBB) | IBUS_NO_VBB | 10 | µA | VBB = GND, 0 < VBUS < 18V, (Note 2) | 12 | ||
| Slave Termination | RSLAVE | 20 | 30 | 60 | k | 12 | |
| Capacitance of Slave Node | CSLAVE | 100 | pF | Note 3 | 12 | ||
| Slope Rising and Falling Edges | tSLOPE | 3.5 | 22.5 | µs | 7.3V ≤ VBB ≤ 18V | 13 | |
| Propagation Delay of Transmitter | tTRANSPD | 4 | µs | tTRANSPD = max (tTRANSPDR or tTRANSPDF) | 13 | ||
| Propagation Delay of Receiver | tRECPD | 6 | µs | tRECPD = max (tRECPDR or tRECPDF) | 13 | ||
| Symmetry of Propagation Delay of Receiver Rising Edge w.r.t. Falling Edge | tRECSYM | -2 | 2 | µs | tRECSYM = max (tRECPDF - tRECPDR) | 13 | |
| Symmetry of Propagation Delay of Transmitter Rising Edge w.r.t. Falling Edge | tTRANSSYM | -2 | 2 | µs | tTRANSSYM = max (tTRANSPDF - tTRANSPDR) | 13 | |
| Duty Cycle 1 | D1 | 0.396 | @20.0 kbit/sec; VBB = 7.0V - 18V; tBIT = 50 µs | 13 | |||
| Duty Cycle 2 | D2 | 0.581 | @20.0 kbit/sec; VBB = 7.6V - 18V; tBIT = 50 µs | 13 | |||
| Duty Cycle 3 | D3 | 0.417 | @10.4 kbit/sec; VBB = 7.0V - 18V; tBIT = 96 µs | 13 | |||
| Duty Cycle 4 | D4 | 0.59 | @10.4 kbit/sec; VBB = 7.6V - 18V; tBIT = 96 µs | 13 | |||
| Bus Activity Debounce time | tBDB | 30 | 70 | 125 | µs | 13 | |
| Bus Activity to VREN on | tBACTVE | 10 | 60 | 110 | µs | 13 | |
| WAKE to VREN on | tWAKE | 150 | µs | 13 | |||
| Chip Select to VREN on | tCSOR | 150 | µs | VREN floating | 13 | ||
| Chip Select to VREN off | tCSPD | 200 | µs | VREN floating | 13 | ||
| Short-Circuit Recovery Time | tTHERM | 1.5 | 5 | ms | 14 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | SN = 8-Lead Plastic Small Outline, Narrow 3.90 mm Body (SOIC) | 29 |
CAD (KiCad official)
- Symbol:
MCP2003BT-H - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp2003bt-h-etched.step/mcp2003bt-h-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp2003bt-h.step/mcp2003bt-h.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (32 pp, sha256
d89c165048b73ca3, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).