# MCP1825T-5002E

**Microchip Tech** · Linear Voltage Regulators (LDO) · SOT-223-5

MCP1825T-5002E from Microchip Tech, in a SOT-223-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SHDN | input | Active-low shutdown control input: logic-high enables the LDO output, and pulling it to logic-low disables the output, drives PWRGD low, and puts the LDO in a shutdown state with typical quiescent current of 0.1 µA. |
| 2 | VIN | power_in | Input voltage supply, with an operating input range of 2.1V to 6.0V; a typical input capacitance of 1 µF to 10 µF is recommended, especially when the source is remote or a battery. |
| 3 | GND | power_in | Ground connection that should be tied to a quiet circuit ground, carrying only the LDO quiescent current (typically 120 µA). |
| 4 | VOUT | power_out | Regulated output voltage of the LDO, which requires a minimum output capacitance of 1.0 µF for stability. |
| 5 | PWRGD | output | Open-drain power good output that indicates when the output is within 92% (typical) of its regulated value, with a typical 2% hysteresis and a fixed 110 µs (typical) power-up delay. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-223-5 |
| Category | Power Management ICs |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage Regulation (fixed output, relative to VR) | VOUT | -2.5 | 0.5 | 2.5 | % | Fixed 5.0V version; min VR-2.5%, typ VR ±0.5%, max VR+2.5% (Note 2) | 7 |
| Input Operating Voltage | VIN | 2.1 |  | 6 | V | Note 1 | 7 |
| Input Quiescent Current | Iq |  | 120 | 220 | µA | IL = 0 mA, VOUT = 0.8V to 5.0V | 7 |
| Input Quiescent Current for SHDN Mode | ISHDN |  | 0.1 | 3 | µA | SHDN = GND | 7 |
| Maximum Output Current | IOUT | 500 |  |  | mA | VIN = 2.1V to 6.0V; VR = 0.8V to 5.0V, Note 1 | 7 |
| Line Regulation | ΔVOUT/(VOUT x ΔVIN) | -0.16 | 0.05 | 0.16 | %/V | (Note 1) ≤ VIN ≤ 6V | 7 |
| Load Regulation | ΔVOUT/VOUT | -1 | 0.5 | 1 | % | IOUT = 1 mA to 500 mA, (Note 4) | 7 |
| Dropout Voltage | VDROPOUT |  | 210 | 350 | mV | Note 5, IOUT = 500 mA, VIN(MIN) = 2.1V | 8 |
| PWRGD Input Voltage Operating Range | VPWRGD_VIN | 1 |  | 6 | V | TA = +25°C | 8 |
| PWRGD Input Voltage Operating Range |  | 1.2 |  | 6 | V | TA = -40°C to +125°C | 8 |
| PWRGD Threshold Voltage (referenced to VOUT, falling edge) | VPWRGD_TH | 90 | 92 | 94 | %VOUT | VOUT >= 2.5V Fixed | 8 |
| PWRGD Threshold Hysteresis | VPWRGD_HYS | 1 | 2 | 3 | %VOUT |  | 8 |
| PWRGD Output Voltage Low | VPWRGD_L |  | 0.2 | 0.4 | V | IPWRGD SINK = 1.2 mA, ADJ = 0V | 8 |
| Shutdown Logic High Input | VSHDN-HIGH | 45 |  |  | %VIN | VIN = 2.1V to 6.0V | 8 |
| Shutdown Logic Low Input | VSHDN-LOW |  |  | 15 | %VIN | VIN = 2.1V to 6.0V | 8 |
| SHDN Input Leakage Current | SHDNILK | -0.1 | 0.001 | 0.1 | µA | VIN = 6V, SHDN = VIN, SHDN = GND | 8 |
| Operating Junction Temperature Range | TJ | -40 |  | 125 | °C | Steady State | 10 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C | Transient | 10 |
| Storage Temperature Range | TA | -65 |  | 150 | °C |  | 10 |
| ESD protection, HBM |  | 4 |  |  | kV | HBM, all pins | 7 |
| ESD protection, MM |  | 300 |  |  | V | MM, all pins | 7 |
| Output Capacitance (recommended) |  | 1 |  | 22 | µF | Section 4.3: minimum for stability, maximum recommended | 17 |
| Output Capacitor ESR (aluminum-electrolytic) | ESR |  |  | 1 | Ω | Section 4.3, must be no greater than 1 ohm | 17 |
| Input Capacitance (recommended) |  | 1 |  | 4.7 | µF | Section 4.4, minimum of 1.0 µF to 4.7 µF recommended | 18 |
| Thermal Resistance, junction to ambient, 5LD SOT-223 | θJA |  | 62 |  | °C/W | EIA/JEDEC JESD51-751-7, 4 Layer Board | 10 |
| Thermal Resistance, junction to case, 5LD SOT-223 | θJC |  | 15 |  | °C/W | EIA/JEDEC JESD51-751-7, 4 Layer Board | 10 |

## CAD (KiCad official)

- Symbol: `MCP1825T-5002E`
- Footprint: `Package_TO_SOT_SMD:SOT-223-5`
- 3D model: SOT-223-5, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.45 mm nominal SOT height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `mcp1825t-5002e-etched.step` / `mcp1825t-5002e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp1825t-5002e.step` / `mcp1825t-5002e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/mcp1825t-5002e-datasheet.pdf) (38 pp, sha256 `e9a345781e0f044a`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mcp1825t-5002e-datasheet.pdf)