MCP1824T-ADJE from Microchip Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Input voltage supply with an operating range of 2.1V to 6.0V; an input capacitor of 1 µF to 10 µF is recommended for most applications.
2	GND	power_in	Ground pin should be tied to an electrically quiet circuit ground, as it only conducts the LDO ground current.
3	SHDN	input	Active-low shutdown control input; a logic-low disables the LDO output and drives PWRGD low, reducing quiescent current to a typical 0.1 µA.
4	ADJ	input	Output voltage adjust input with a nominal voltage of 0.41V, set by an external resistor divider to any output between 0.8V and 5.0V.
5	VOUT	power_out	Regulated output voltage that requires a minimum output capacitance of 1.0 µF for LDO stability.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	SOT-23-5
Category	Power Management ICs
Pins	5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Operating Voltage	VIN	2.1		6	V		7
Output Voltage Range	VOUT	0.8		5	V		7
Input Quiescent Current	Iq		120	220	µA	IL = 0 mA, VOUT = 0.8V to 5.0V	7
Input Quiescent Current for SHDN Mode	ISHDN		0.1	3	µA	SHDN = GND	7
Maximum Continuous Output Current	IOUT	300			mA	VIN = 2.1V to 6.0V, VR = 0.8V to 5.0V	7
Line Regulation	ΔVOUT/(VOUT x ΔVIN)		0.05	0.17	%/V	(Note 1) ≤ VIN ≤ 6V	7
Load Regulation	ΔVOUT/VOUT	-1	0.5	1	%	IOUT = 1 mA to 300 mA, (Note 4)	7
Output Short Circuit Current	IOUT_SC		720		mA	RLOAD < 0.1Ω, Peak Current	7
Dropout Voltage	VDROPOUT		200	320	mV	Note 5, IOUT = 300 mA, VIN(MIN) = 2.1V	7
Maximum Pulsed Output Current	IPULSE		500		mA	VIN = 2.1V to 6.0V, VR = 0.8V to 5.0V, Duty Cycle ≤ 60%, Period < 10 ms	7
Maximum Pulsed Output Duty Cycle	IPULSE_DUTY			60	%	VIN = 2.1V to 6.0V, VR = 0.8V to 5.0V, IOUT = 500 mA, Period < 10 ms	8
Maximum Pulsed Output Period	IPULSE_PERIOD			10	ms	VIN = 2.1V to 6.0V, VR = 0.8V to 5.0V, IOUT = 500 mA	8
Adjustable Output Voltage Range	VOUT_ADJ	0.8		5.5	V		8
Adjust Pin Reference Voltage	VADJ	0.402	0.41	0.418	V	VIN = 2.1V to VIN = 6.0V, IOUT = 1 mA	8
Adjust Pin Leakage Current	IADJ	-10	0.01	10	nA	VIN = 6.0V, VADJ = 0V to 6V	8
Adjust Temperature Coefficient	TCVOUT		40		ppm/°C	Note 3	8
PWRGD Input Voltage Operating Range	VPWRGD_VIN	1		6	V	TA = +25°C	8
PWRGD Input Voltage Operating Range	VPWRGD_VIN	1.2		6	V	TA = -40°C to +125°C, For VIN < 2.1V, ISINK = 100 µA	8
PWRGD Threshold Voltage (Referenced to VOUT)	VPWRGD_TH	89	92	95	%VOUT	Falling Edge, VOUT < 2.5V Fixed, VOUT = Adj.	8
PWRGD Threshold Hysteresis	VPWRGD_HYS	1	2	3	%VOUT		8
PWRGD Output Voltage Low	VPWRGD_L		0.05	0.4	V	IPWRGD SINK = 1.2 mA, ADJ = 0V	8
PWRGD Output Current Sink Capability	IPWRGD	1.2	6		mA	VPWRGD = 0.200V	8
PWRGD Leakage	PWRGD_LK		1		nA	VPWRGD = VIN = 6.0V	8
PWRGD Time Delay	TPG		110		µs	Rising Edge, RPULLUP = 10 kΩ	8
Detect Threshold to PWRGD Active Time Delay	TVDET-PWRGD		200		µs	VOUT = VPWRGD_TH + 50 mV to VPWRGD_TH - 50 mV	9
Shutdown Input Logic High	VSHDN-HIGH	45			%VIN	VIN = 2.1V to 6.0V	9
Shutdown Input Logic Low	VSHDN-LOW			15	%VIN	VIN = 2.1V to 6.0V	9
SHDN Input Leakage Current	SHDNILK	-0.1	0.001	0.1	µA	VIN = 6V, SHDN =VIN, SHDN = GND	9
Output Delay From SHDN	TOR		100		µs	SHDN = GND to VIN, VOUT = GND to 95% VR	9
Output Noise	eN		2		µV/√Hz	IOUT = 200 mA, f = 1 kHz, COUT = 10 µF (X7R Ceramic), VOUT = 2.5V	9
Power Supply Ripple Rejection Ratio	PSRR		55		dB	f = 100 Hz, IOUT = 10 mA, VINAC = 200 mV pk-pk, CIN = 0 µF	9
Thermal Shutdown Temperature	TSD		150		°C	IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V	9
Thermal Shutdown Hysteresis	ΔTSD		10		°C	IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V	9
Operating Junction Temperature Range	TJ	-40		125	°C	Steady State	10
Maximum Junction Temperature	TJ			150	°C	Transient	10
Storage Temperature Range	TA	-65		150	°C		10
Thermal Resistance, Junction to Ambient, 5LD SOT-23	θJA		256		°C/W	EIA/JEDEC JESD51-7, 4 Layer Board	10
Thermal Resistance, Junction to Case, 5LD SOT-23	θJC		81		°C/W	EIA/JEDEC JESD51-7, 4 Layer Board	10

CAD (KiCad official)

Symbol: MCP1824T-ADJE
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT-23-5 (KiCad packages3D, STEP)
3D model files: mcp1824t-adje-etched.step / mcp1824t-adje-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp1824t-adje.step / mcp1824t-adje.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (34 pp, sha256 dda3986a6bed8be8, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MCP1824T-ADJE

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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