component

MCP1711T-25I

Public Made by Adom

by adom

Microchip Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)mcp1711t-25ifactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
mcp1711t-25i / README.md
History Download
Ray Publish 0.1.0 383709c 16d ago

MCP1711T-25I

Microchip Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

MCP1711T-25I from Microchip Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Unregulated input supply; the datasheet gives an input voltage range of 1.4 V to 6.0 V, and a 0.1 µF capacitor is sufficient for stability in most applications.
2 GND power_in Regulator ground that the LDO output is referenced to; only the LDO bias current flows through this pin, and the GND trace to the load ground should be kept as short as possible.
3 SHDN input Active-high shutdown input that enables the output at a logic high of at least 0.91 V and disables it at a logic low of at most 0.38 V; the output becomes unstable if this pin is left floating.
4 NC unconnected Not connected internally; the datasheet says this pin should be left floating or connected to the ground plane.
5 VOUT power_out Regulated output of 2.5 V nominal for this -25 variant (2.4750 V to 2.5250 V), with a maximum output current of 150 mA; the positive terminal of the output capacitor should be placed as close to this pin as possible.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 1.4 6 V IOUT = 1 µA 3
Output voltage (2.5 V option) VOUT 2.475 2.525 V VR ≥ 2.0V 4
Maximum output current IOUT 150 mA 3
Load regulation VOUT -16 3 16 mV 1 µA ≤ IOUT ≤ 1 mA 3
Load regulation VOUT -50 17 50 mV 1 mA ≤ IOUT ≤ 150 mA 3
Dropout voltage VDROPOUT1 0.26 0.4 V IOUT = 50 mA 3
Dropout voltage VDROPOUT2 0.67 0.92 V IOUT = 150 mA 3
Input quiescent current Iq 0.65 1.5 µA 1.9V ≤ VR < 4.0V 3
SHDN-mode input quiescent current ISHDN 0.01 0.1 µA VIN = 6.0V, VSHDN = VIN 3
Line regulation VOUT/(VIN x VOUT) -0.13 0.01 0.13 %/V IOUT = 1 µA, VR + 0.5V ≤ VIN ≤ 6.0V 3
Line regulation VOUT/(VIN x VOUT) -0.19 0.01 0.19 %/V IOUT = 1 mA, VR ≥ 1.2V, VR + 0.5V ≤ VIN ≤ 6.0V 3
Output voltage temperature coefficient VOUT/(T x VOUT) -50 50 ppm/°C IOUT = 10 mA, -40°C ≤ TA ≤ +85°C 4
Current limit ILIMIT 150 270 mA VOUT = 0.95 x VR 4
Output auto-discharge resistance RDCHG 280 450 640 SHDN = GND, VOUT = VR 4
SHDN logic high input voltage VSHDN-HIGH 0.91 6 V 4
SHDN logic low input voltage VSHDN-LOW 0 0.38 V 4
SHDN high-level input current ISHDN-HIGH -0.1 0.1 µA VIN = 6.0V 4
SHDN low-level input current ISHDN-LOW -0.1 0.1 µA VIN = 6.0V, SHDN = GND 4
Input voltage (absolute maximum) VIN 6.5 V 3
VIN, SHDN voltage (absolute maximum) VIN, SHDN -0.3 6.5 V 3
Output voltage (absolute maximum) VOUT -0.3 V Maximum is the lower of VIN + 0.3V and +6.5V (note 2) 3
Power dissipation, 5-lead SOT-23 PD 600 mW JEDEC 51-7 FR-4 board with thermal vias 3
Power dissipation, 5-lead SOT-23 PD 250 mW Single-layer PCB with minimal copper, no additional cooling (note 3) 3
Storage temperature range TA -55 125 °C 5
ESD protection, all pins -1 1 kV HBM 3
ESD protection, all pins -200 200 V MM 3
Operating ambient temperature range TA -40 85 °C 5
Operating junction temperature range TJ -40 125 °C 5
Thermal resistance, junction to ambient, 5-lead SOT-23 JA 166.67 °C/W JEDEC 51-7 FR4 board with thermal vias 5
Thermal resistance, junction to ambient, 5-lead SOT-23 JA 400 °C/W Single-layer PCB with minimal copper, no additional cooling (note 2) 5
Thermal resistance, junction to case, 5-lead SOT-23 JC 81 °C/W 5

CAD (KiCad official)

  • Symbol: MCP1711T-25I
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: mcp1711t-25i-etched.step / mcp1711t-25i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp1711t-25i.step / mcp1711t-25i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (36 pp, sha256 f62007b2dfbc5196, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF