MCP16502TAA-E from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	nINTO	output	Active-low, open-drain interrupt output to the MPU.
2	nRSTO	output	Active-low, open-drain reset output.
3	SGND	power_in	Signal ground; connect to the reference ground plane.
4	SVIN	power_in	Input voltage for the analog control circuitry; decouple SVIN to SGND with a 1 µF (minimum) ceramic capacitor.
5	SDA	bidirectional	I2C interface serial data.
6	SCL	input	I2C interface serial clock.
7	nSTRTO	output	Active-low, open-drain start event output that is asserted low whenever nSTRT is low.
8	PWRHLD	input	Power hold input, typically asserted high by the MPU to maintain power after start-up and asserted low by the MPU to initiate a PMIC shutdown sequence.
9	OUT1	input	Output sensing for Buck Channel 1; connect to the regulation point for VOUT1.
10	PVIN1	power_in	Power input voltage of Buck Channel 1; connect a ceramic capacitor from PVIN1 to PGND1 to localize pulsed current loops and decouple switching noise.
11	SW1	output	Switch node of Buck Channel 1 connecting the internal power MOSFETs to the external inductor.
12	PGND1	power_in	Power ground of Buck Channel 1.
13	PGND2	power_in	Power ground of Buck Channel 2.
14	SW2	output	Switch node of Buck Channel 2 connecting the internal power MOSFETs to the external inductor.
15	PVIN2	power_in	Power input voltage of Buck Channel 2; connect a ceramic capacitor from PVIN2 to PGND2 to localize pulsed current loops and decouple switching noise.
16	OUT2	input	Output sensing for Buck Channel 2; connect to the regulation point for VOUT2.
17	SELV2	input	Buck Channel 2 output voltage selection pin; three-state input.
18	SELVL1	input	LDO1 default output voltage selection pin; three-state input.
19	LOUT1	power_out	LDO1 output; decouple LOUT1 to ground with a 2.2 µF (minimum) ceramic capacitor.
20	LVIN	power_in	Input voltage for LDO1 and LDO2; decouple LVIN to ground with a 2.2 µF (minimum) ceramic capacitor.
21	LOUT2	power_out	LDO2 output; if LDO2 is in use, decouple LOUT2 to SGND with a 2.2 µF (minimum) ceramic capacitor.
22	LPM	input	Low-power mode input which, in combination with PWRHLD and HPM, defines the power mode status of the MCP16502.
23	HPM	input	High-performance mode input which, in combination with PWRHLD and LPM, defines the power mode status of the MCP16502; connect to ground if not used.
24	nSTRT	input	Start event input; drive low to initiate a start-up sequence, with an internal pull-up and an optional capacitor for automatic power-up on VIN ramp.
25	OUT3	input	Output sensing for Buck Channel 3; connect to the regulation point for VOUT3.
26	PVIN3	power_in	Power input voltage of Buck Channel 3; connect a ceramic capacitor from PVIN3 to PGND3 to localize pulsed current loops and decouple switching noise.
27	SW3	output	Switch node of Buck Channel 3 connecting the internal power MOSFETs to the external inductor.
28	PGND3	power_in	Power ground of Buck Channel 3.
29	PGND4	power_in	Power ground of Buck Channel 4.
30	SW4	output	Switch node of Buck Channel 4 connecting the internal power MOSFETs to the external inductor.
31	PVIN4	power_in	Power input voltage of Buck Channel 4; connect a ceramic capacitor from PVIN4 to PGND4 to localize pulsed current loops and decouple switching noise.
32	OUT4	input	Output sensing for Buck Channel 4; connect to the regulation point for VOUT4.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	VQFN-32-EP(5x5)
Category	Power Management ICs
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage Temperature		-65		150	°C		5
SVIN to SGND		-0.3		6	V		5
Power Supply Voltage Pins PVINx to PGNDx		-0.3		6	V		5
Power Supply Voltage Pins PVINx to SVIN		-0.3		0.3	V		5
OUTx Sense Pins to SGND		-0.3		6	V		5
PGNDx to SGND		-0.3		0.3	V		5
SDA, SCL, LPM, HPM, PWRHLD, nRSTO, nSTRTO, nINTO to SGND		-0.3		6	V		5
Maximum Junction Temperature				150	°C		5
Operating Junction Temperature Range	TJ	-40		125	°C	Steady state	11
Supply Voltage Range	VIN	2.7		5.5	V		5
Undervoltage Lockout Threshold	VUVLO_TH	2.4	2.55	2.7	V	Turn-on	5
Shutdown (Off) Current	ISHDN		7	11	µA	PWRHLD = LPM = HPM = 0, nSTRT, nRSTO, nSTRTO, nINTO floating, VIN = 5.5V	5
Shutdown (Off) Current, TJ = -40°C to +105°C	ISHDN_105		6	10	µA	PWRHLD = LPM = HPM = 0, nSTRT, nRSTO, nSTRTO, nINTO floating, VIN = 4.5V, TJ = -40°C to +105°C	5
Hibernate Mode Non-Switching Quiescent Current	IQNS_HIB		120	150	µA	IOUT2 = 0 mA, Buck2 on, all other channels off, VOUT2 >VOUT2_NOM, LPM = 1, PWRHLD = HPM = 0	5
Time Base Accuracy	ACC_TB	-10		10	%	FSD[1:0] = 00, 01	6
Buck1 Input Operating Voltage Range	VPVIN1	2.7		5.5	V		6
Buck1 Output Voltage Range	VOUT1	1.2		3.7	V	50 mV steps	6
PVIN1 Shutdown Current	IPVIN1_SHDN		0.05	2	µA	Regulator disabled, VPVIN1 = 5V	6
Buck1 Output Voltage Accuracy, FPWM	ACC_OUTPWM1	-2		2	%	IOUT1 = 0 mA	6
Buck1 Output Voltage Accuracy, Auto-PFM	ACC_OUTPFM1	-2		2	%	IOUT1 = 0 mA, B1HCEN = 0	6
Buck1 Switching Frequency	fsw	1.8	2	2.2	MHz	FPWM, FSD[1:0] = 00, 01	7
Buck1 Maximum Duty Cycle	DMAX	100			%	Functionality test	7
Buck1 High-Side Switch On-Resistance	RDsonP1		140	160	mΩ	PVIN1 = SVIN = 3.6V	7
Buck1 Low-Side Switch On-Resistance	RDsonN1		120	140	mΩ	PVIN1 = SVIN = 3.6V	7
Buck1 POK (Power OK) Threshold	POK_TH1	90	92.5	95	%	OUT1 rising, % of VOUT1_NOM	7
Buck1 Start-up POK Bypass Threshold	VPOKB_TH_B1	360	400	440	mV	PVIN1, OUT1, OUT1 rising, PVIN1 = 3.0V, VOUT1_NOM = 3.3V	7
Buck1 High-Side Peak Current Limit (Cycle by Cycle)	ILIM_HS1	1.2	1.8	2.4	A		7
Buck1 Low-Side Negative Peak Current Limit (FPWM)	ILIM_NEG1	-1.4	-1	-0.8	A		8
Buck1 Zero Current Detection Threshold	IZCD1	0	50	110	mA		8
Buck2, Buck3, Buck4 Input Operating Voltage Range	VPVINx	2.7		5.5	V		8
Buck2, Buck3, Buck4 Output Voltage Range	VOUTx	0.6		1.85	V	25 mV steps	8
PVINx Shutdown Current	IPVINx_SHDN		0.05	2	µA	Regulator disabled, PVINx = 5V	8
Buck2-4 Output Voltage Accuracy, FPWM	ACC_OUTPWMx	-1		1	%	IOUTx = 0 mA, 0.9V ≤ VOUTx ≤ 1.3V	8
Buck2-4 Output Voltage Accuracy, FPWM	ACC_OUTPWMx	-1.5		1.5	%	IOUTx = 0 mA, VOUTx < 0.9V or VOUTx > 1.3V	8
Buck2-4 Output Voltage Accuracy, Auto-PFM	ACC_OUTPFMx	-1		1	%	IOUTx = 0 mA, 0.9V ≤ VOUTx ≤ 1.3V	8
Buck2-4 Output Voltage Accuracy, Auto-PFM	ACC_OUTPFMx	-1.5		1.5	%	IOUTx = 0 mA, VOUTx < 0.9V or VOUTx > 1.3V	8
Buck2-4 Switching Frequency	fsw	1.8	2	2.2	MHz	FPWM, FSD[1:0] = 00, 01	8
Buck2-4 Maximum Duty Cycle	DMAX	100			%	Functionality test	8
Buck2-4 High-Side Switch On-Resistance	RDSonPx		140	160	mΩ	PVINx = SVIN = 3.6V	8
Buck2-4 Low-Side Switch On-Resistance	RDSonNx		120	140	mΩ	PVINx = SVIN = 3.6V	8
Buck2-4 POK (Power OK) Threshold	POK_THx	90	92.5	95	%	OUTx rising, % of VOUTx(NOM)	8
Buck2-4 High-Side Peak Current Limit (Cycle-by-Cycle)	ILIM_HSx	1.2	1.8	2.4	A		9
Buck2-4 Low-Side Negative Peak Current Limit (FPWM)	ILIM_NEGx	-1.4	-1	-0.8	A		9
LDO Input Operating Voltage Range	VLVIN	2.7		5.5	V		9
LDO1, LDO2 Output Voltage Range	VLOUTx	1.2		3.7	V		9
LDO Stable Output Capacitor Range	CLOUTx	2.2		20	µF	ILOUT1,2 ≤ 150 mA, application requirement	9
LDO Stable Output Capacitor Range	CLOUTx	4.7		20	µF	ILOUT1,2 ≤ 300 mA, application requirement	9
LDO Output Voltage Accuracy	ACC_LOUTx	-3		3	%	LVIN = SVIN = 3.6V, ILOUT1,2 = 0.1 mA	9
LDO Dropout Voltage	VDOx		170	500	mV	ILOUT1,2 = 300 mA	9
LDO POK (Power OK) Threshold	POK_THL	90	92.3	95	%	LOUT1,2 rising, % of VLOUT1,2(NOM)	10
LDO Start-up POK Bypass Threshold	VPOKB_TH_Lx	400	500	600	mV	LVIN, LOUTx, LOUTx rising, LVIN = 3.0V, VLOUTx_NOM = 3.3V	10
LDO Current Limit	ILIM_LOUTx	310	420	550	mA	SVIN = LVIN = 4.5V, VLOUT1,2 = 80% of nominal	10
PWRHLD, LPM, HPM Logic High Input Voltage	VIH_x	1.5			V	SVIN = 3.6V-5.5V	11
PWRHLD, LPM, HPM Logic Low Input Voltage	VIL_x			0.4	V	SVIN = 3.6V-5.5V	11
PWRHLD, LPM, HPM Input Leakage Current	Ilkg_x	-1		1	µA		11
nRSTO, nSTRTO, nINTO Output Voltage Low	VOL_x			0.4	V	SVIN = 3.6V-5.5V, IOL = 2 mA	11
nRSTO, nSTRTO, nINTO Leakage Current	Ilkg_x			1	µA	5.5V applied, output driver off	11
SDA, SCL Logic High Input Voltage	VIH_x	1.5			V	SVIN = 3.6V-5.5V	11
SDA, SCL Logic Low Input Voltage	VIL_x			0.4	V	SVIN = 3.6V-5.5V	11
SDA, SCL Leakage Current	Ilkg_x			1	µA	SDA driver off, VSDA = 5.5V, VSCL= 5.5V	11
SDA Output Voltage Low	VOL			0.4	V	SVIN = 3.6V-5.5V, IOL = 20 mA	11
SELVx Input Leakage Current High	IlkgH_SELVx		0.01	1	µA	SELVx = SVIN, 0.4V	11
SELVx Input Leakage Current Low	IlkgL_SELVx	-1	0.01		µA	SELVx = 0.4V	11
Package Thermal Resistance, Junction to Ambient	θJA		25.8		°C/W		11

CAD (KiCad official)

Symbol: MCP16502TAA-E
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: mcp16502taa-e-etched.step / mcp16502taa-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp16502taa-e.step / mcp16502taa-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (88 pp, sha256 6c8710c7a146076c, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MCP16502TAA-E

Verified MCP16502TAA-E

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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