component
MCP16501TE-E
Public Made by Adomby adom
Microchip Tech Power Management - Specialized, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP16501TE-E
Microchip Tech · Power Management - Specialized · VQFN-24(4x4)
MCP16501TE-E from Microchip Tech, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | input | Output sensing for Buck Channel 1; connect to the regulation point for VOUT1. |
| 2 | nRSTO | output | Active-low, open-drain reset output. |
| 3 | PWRHLD | input | Power hold input, typically driven high by the MPU to maintain power after start-up; the MPU drives it low to initiate a PMIC shutdown sequence. |
| 4 | LPM | input | Low-power mode input which, in combination with PWRHLD, defines the power mode status of the MCP16501. |
| 5 | nSTRTO | output | Active-low, open-drain start event output that is asserted low whenever nSTRT is low. |
| 6 | OUT2 | input | Output sensing for Buck Channel 2; connect to the regulation point for VOUT2. |
| 7 | PVIN2 | power_in | Power input voltage of Buck Channel 2; connect a ceramic capacitor from PVIN2 to PGND2 to localize pulsed current loops and decouple switching noise. |
| 8 | SW2 | output | Switch node of Buck Channel 2 connecting the internal power MOSFETs to the external inductor. |
| 9 | PGND2 | power_in | Power ground of Buck Channel 2. |
| 10 | PGND3 | power_in | Power ground of Buck Channel 3. |
| 11 | SW3 | output | Switch node of Buck Channel 3 connecting the internal power MOSFETs to the external inductor. |
| 12 | PVIN3 | power_in | Power input voltage of Buck Channel 3; connect a ceramic capacitor from PVIN3 to PGND3 to localize pulsed current loops and decouple switching noise. |
| 13 | OUT3 | input | Output sensing for Buck Channel 3; connect to the regulation point for VOUT3. |
| 14 | nSTRT | input | Start event input; driving it low initiates a start-up sequence, it is pulled up internally, and a capacitor on this pin can auto-initiate power-up when the main supply rises. |
| 15 | SELV3 | input | Buck Channel 3 output voltage selection pin, a three-state input. |
| 16 | SGND | power_in | Signal ground; connect to the reference ground plane. |
| 17 | VIN | power_in | Input voltage for the LDO and analog control circuitry; decouple VIN to SGND with a 2.2 µF (minimum) ceramic capacitor. Input range is 2.7 V to 5.5 V per the features list. |
| 18 | LOUT | power_out | LDO output; decouple LOUT to ground with a 2.2 µF (minimum) ceramic capacitor. |
| 19 | LFB | input | LDO feedback pin; connect to an external resistor divider to LOUT for output voltage adjustment. |
| 20 | SELV2 | input | Buck Channel 2 output voltage selection pin, a three-state input. |
| 21 | LEN | input | LDO enable input. |
| 22 | PGND1 | power_in | Power ground of Buck Channel 1. |
| 23 | SW1 | output | Switch node of Buck Channel 1 connecting the internal power MOSFETs to the external inductor. |
| 24 | PVIN1 | power_in | Power input voltage of Buck Channel 1; connect a ceramic capacitor from PVIN1 to PGND1 to localize pulsed current loops and decouple switching noise. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | VQFN-24(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to SGND | -0.3 | 6 | V | 5 | |||
| Power Supply Voltage Pins PVINx to PGNDx | -0.3 | 6 | V | 5 | |||
| Power Supply Voltage Pins PVINx to VIN | -0.3 | 0.3 | V | 5 | |||
| LOUT Pin to GND | -0.3 | V | Max printed as VVIN + 0.3V | 5 | |||
| LFB Sense Pins to SGND | -0.3 | V | Max printed as VVIN + 0.3V | 5 | |||
| OUTx Sense Pins to SGND | -0.3 | 6 | V | 5 | |||
| Output Switch Voltage SWx to PGNDx | -0.3 | V | Max printed as VPVINx + 0.3V | 5 | |||
| PGNDx to SGND | -0.3 | 0.3 | V | 5 | |||
| nSTRT, SELV2, SELV3 to SGND | -0.3 | V | Max printed as VVIN + 0.3V | 5 | |||
| LPM, LEN, PWRHLD, nRSTO, nSTRTO to SGND | -0.3 | 6 | V | 5 | |||
| Maximum Junction Temperature | 150 | °C | 5 | ||||
| Storage Temperature | -65 | 150 | °C | 5 | |||
| ESD Protection HBM | 2 | kV | 5 | ||||
| ESD Protection CDM | 750 | V | 5 | ||||
| Supply Voltage Range | VIN | 2.7 | 5.5 | V | 5 | ||
| Undervoltage Lockout Threshold | VUVLO_TH | 2.4 | 2.55 | 2.7 | V | Turn-on | 5 |
| Shutdown (OFF) Current | ISHDN | 7 | 10 | µA | PWRHLD = LPM = 0, nSTRT, nRSTO, nSTRTO floating, VIN = 5.5V | 5 | |
| Shutdown (OFF) Current, TJ = -40°C to +105°C | ISHDN_105 | 4.5 | 6 | µA | PWRHLD = LPM = 0, nSTRT, nRSTO, nSTRTO floating, VIN = 4.5V, TJ = -40°C to +105°C | 5 | |
| Hibernate Mode Non-Switching Quiescent Current | IQNS_HIB1 | 110 | 150 | µA | IOUT2 = 0 mA, Buck2 ON, all other channels off, VOUT2 >VOUT2_NOM, LPM = 1, PWRHLD = 0 | 5 | |
| Input Operating Voltage Range (Buck1) | VPVIN1 | 2.7 | 5.5 | V | 6 | ||
| PVIN1 Shutdown Current | IPVIN1_SHDN | 0.05 | 2 | µA | Regulator disabled, VPVIN1 = 5V | 6 | |
| Output Voltage Accuracy, FPWM (Buck1) | ACC_OUTPWM1 | -2 | 2 | % | IOUT1 = 0 mA | 6 | |
| Output Voltage Accuracy, Auto-PFM (Buck1) | ACC_OUTPFM1 | -2 | 2 | % | IOUT1 = 0 mA, HCM OFF | 6 | |
| Hysteretic Control Mode Upper Regulation Threshold, Auto-PFM (MCP16501E only) | HCM_TH | 1.7 | 2.9 | 4.3 | % | IOUT1 = 0 mA, PWRHLD = LPM = 1, VIN = PVIN1 = 1.06 x VOUT1_NOM, OUT1 rising, % of VOUT1_NOM | 6 |
| Hysteretic Control Mode Enable Threshold, Auto-PFM (MCP16501E only) | HCM_EN | 5 | 9 | 13 | % | IOUT1 = 0 mA, PWRHLD = LPM = 1, VIN = PVIN1 falling, % of VOUT1_NOM | 7 |
| Switching Frequency (Buck1) | fsw | 1.8 | 2 | 2.2 | MHz | FPWM | 7 |
| Maximum Duty Cycle (Buck1) | DMAX | 100 | % | Functionality test | 7 | ||
| High-Side Switch On-Resistance (Buck1) | RDSonP1 | 140 | 160 | mΩ | PVIN1 = VIN = 3.6V | 7 | |
| Low-Side Switch On-Resistance (Buck1) | RDSonN1 | 120 | 140 | mΩ | PVIN1 = VIN = 3.6V | 7 | |
| Start-up POK Bypass Threshold (Buck1) | VPOKB_TH_B1 | 360 | 400 | 440 | mV | PVIN1, OUT1, OUT1 rising, PVIN1 = 3.0V, VOUT1_NOM = 3.3V | 7 |
| High-Side Peak Current Limit (Cycle by Cycle) (Buck1) | ILIM_HS1 | 1.2 | 1.8 | 2.4 | A | 7 | |
| Low-Side Negative Peak Current Limit (FPWM) (Buck1) | ILIM_NEG1 | -1.4 | -1 | -0.8 | A | 7 | |
| Zero Current Detection Threshold (Buck1) | IZCD1 | 0 | 50 | 110 | mA | 7 | |
| PVINx Shutdown Current (Buck2, Buck3) | IPVINx_SHDN | 0.05 | 2 | µA | Regulator disabled, PVINx = 5V | 7 | |
| Output Voltage Accuracy, FPWM (Buck2, Buck3) | ACC_OUTPWMx | -1 | 1 | % | IOUTx = 0 mA, 0.9V ≤ VOUTx ≤ 1.3V | 7 | |
| Output Voltage Accuracy, FPWM (Buck2, Buck3) | ACC_OUTPWMx | -1.5 | 1.5 | % | IOUTx = 0 mA, VOUTx < 0.9V or VOUTx > 1.3V | 7 | |
| Output Voltage Accuracy, Auto-PFM (Buck2, Buck3) | ACC_OUTPFMx | -1 | 1 | % | IOUTx = 0 mA, 0.9V ≤ VOUTx ≤ 1.3V | 7 | |
| Output Voltage Accuracy, Auto-PFM (Buck2, Buck3) | ACC_OUTPFMx | -1.5 | 1.5 | % | IOUTx = 0 mA, VOUTx < 0.9V or VOUTx > 1.3V | 7 | |
| High-Side Switch On-Resistance (Buck2, Buck3) | RDSonPx | 140 | 160 | mΩ | PVINx = VIN = 3.6V | 8 | |
| Low-Side Switch On-Resistance (Buck2, Buck3) | RDSonNx | 120 | 140 | mΩ | PVINx = VIN = 3.6V | 8 | |
| High-Side Peak Current Limit (Cycle-by-Cycle) (Buck2, Buck3) | ILIM_HSx | 1.2 | 1.8 | 2.4 | A | 8 | |
| Low-Side Negative Peak Current Limit (FPWM) (Buck2, Buck3) | ILIM_NEGx | -1.4 | -1 | -0.8 | A | 8 | |
| Zero Current Detection Threshold (Buck2, Buck3) | IZCDx | 0 | 33 | 110 | mA | 8 | |
| Input Operating Voltage Range (LDO) | VLVIN | 2.7 | 5.5 | V | 8 | ||
| Output Voltage Range (LDO) | VLOUT | 0.9 | 3.7 | V | Recommended application settings | 8 | |
| Stable Output Capacitor Range (LDO) | CLOUT | 2.2 | 20 | µF | ILOUT ≤ 150 mA, application requirement | 8 | |
| Stable Output Capacitor Range (LDO) | CLOUT | 4.7 | 20 | µF | ILOUT ≤ 300 mA, application requirement | 8 | |
| Feedback Voltage (LDO) | VLFB | 0.8865 | 0.9 | 0.9135 | V | VIN = 3.6V | 8 |
| Dropout Voltage (LDO) | VDO | 170 | 500 | mV | ILOUT = 300 mA | 8 | |
| Current Limit (LDO) | ILIM_LOUT | 310 | 420 | 550 | mA | VIN = 4.5V, VLOUT = 80% of nominal | 9 |
| LEN Logic High Input Voltage | VIH_LEN | 1.15 | V | 9 | |||
| LEN Logic Low Input Voltage | VIL_LEN | 0.4 | V | 9 | |||
| nSTRT Logic High Input Voltage | VIH_nSTRT | 0.66 | V | VIN = 3.6V, 5.5V; printed as 0.66 x VIN | 9 | ||
| nSTRT Logic Low Input Voltage | VIL_nSTRT | 0.36 | V | VIN = 3.6V, 5.5V; printed as 0.36 x VIN | 9 | ||
| SELV2, SELV3 Low State Threshold Voltage | VILT_SELVx | 0.5 | 1 | V | 9 | ||
| PWRHLD, LPM Logic High Input Voltage | VIH_x | 1.5 | V | VIN = 3.6V, 5.5V | 9 | ||
| PWRHLD, LPM Logic Low Input Voltage | VIL_x | 0.4 | V | VIN = 3.6V, 5.5V | 9 | ||
| nRSTO, nSTRTO Output Voltage Low | VOL_x | 0.4 | V | VIN = 3.6V, 5.5V, IOL = 2 mA | 9 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | Steady state | 9 | |
| Package Thermal Resistance, Junction to Ambient | θJA | 38 | °C/W | 9 |
CAD (KiCad official)
- Symbol:
MCP16501TE-E - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
mcp16501te-e-etched.step/mcp16501te-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp16501te-e.step/mcp16501te-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (42 pp, sha256
5c445b036636e530, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).