component
MCP1624T-I
Public Made by Adomby adom
Microchip Tech DC-DC Converters, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 16d ago |
| viewers | 16d ago |
| mcp1624t-i-etched.glb | 16d ago |
| mcp1624t-i-etched.step | 16d ago |
| mcp1624t-i-hero.glb | 16d ago |
| mcp1624t-i-hero.overlay.json | 16d ago |
| mcp1624t-i.glb | 16d ago |
| mcp1624t-i.kicad_mod | 16d ago |
| mcp1624t-i.kicad_sym | 16d ago |
| mcp1624t-i.lbr | 16d ago |
| mcp1624t-i.step | 16d ago |
| package.json | 16d ago |
| page.json | 16d ago |
| README.md | 16d ago |
MCP1624T-I
Microchip Tech · DC-DC Converters · SOT-23-6
MCP1624T-I from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | passive | Switch node and boost inductor input pin, which carries inductor current with peaks up to 425 mA. |
| 2 | GND | power_in | Ground return pin; keep the input capacitor loop, output capacitor loop and GND trace as short as possible to minimize noise on GND. |
| 3 | EN | input | Logic-level enable input: a level above 90% of VIN enables the regulator and a level below 20% of VIN disables it. |
| 4 | FB | input | Feedback pin for output regulation through a resistor divider, where the FB voltage is 1.21 V (typical) when the output is regulated. |
| 5 | VOUT | power_out | Output voltage pin that connects the integrated P-channel MOSFET to the output capacitor, with the output adjustable from 2.0 V to 5.5 V and the FB divider tied to this pin. |
| 6 | VIN | power_in | Input voltage pin that should be decoupled to GND with a minimum of 4.7 µF. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Minimum start-up voltage | VIN | 0.65 | 0.8 | V | Note 1: 3.3 kΩ resistive load, 3.3V VOUT (1 mA) | 3 | |
| Output voltage regulation range | VOUT | 2 | 5.5 | V | VOUT ≥ VIN; Note 2 | 3 | |
| Maximum output current | IOUT | 50 | mA | 1.5V VIN, 3.3V VOUT | 3 | ||
| Feedback voltage | VFB | 1.12 | 1.21 | 1.299 | V | 3 | |
| Quiescent current, PFM mode | IQPFM | 19 | 30 | µA | Measured at VOUT = 4.0V; EN = VIN, IOUT = 0 mA; Note 3 | 3 | |
| Quiescent current, shutdown | IQSHDN | 0.7 | 2.3 | µA | VOUT = EN = GND; includes N-channel and P-channel switch leakage current | 3 | |
| NMOS switch leakage current | INLK | 0.3 | 1 | µA | VIN = VSW = 5V; VOUT = 5.5V, VEN = VFB = GND | 3 | |
| PMOS switch leakage current | IPLK | 0.05 | 0.2 | µA | VIN = VSW = GND; VOUT = 5.5V | 3 | |
| NMOS peak switch current limit | IN(MAX) | 300 | 425 | mA | Note 5: peak current limit set by design, not production tested | 4 | |
| VOUT accuracy | VOUT% | -7.4 | 7.4 | % | Includes line and load regulation; VIN = 1.5V, IOUT = 50 mA | 4 | |
| Switching frequency | fSW | 370 | 500 | 630 | kHz | 4 | |
| EN input logic high level | VIH | 90 | % | Percent of VIN; IOUT = 1 mA | 4 | ||
| EN input logic low level | VIL | 20 | % | Percent of VIN; IOUT = 1 mA | 4 | ||
| Operating junction temperature range | TJ | -40 | 125 | °C | Steady state | 4 | |
| Storage temperature range | TA | -65 | 150 | °C | Storage | 4 | |
| Maximum junction temperature | TJ | 150 | °C | Transient | 4 | ||
| Ambient temperature with power applied | -40 | 85 | °C | Power applied | 3 | ||
| Input/output voltage absolute maximum | 6.5 | V | EN, FB, VIN, VSW and VOUT to GND | 3 | |||
| ESD HBM protection | 3 | kV | HBM, all pins | 3 | |||
| ESD MM protection | 300 | V | MM, all pins | 3 | |||
| FB input bias current | IVFB | 10 | pA | 3 | |||
| Quiescent current, PWM mode | IQPWM | 220 | µA | Measured at VOUT; EN = VIN, IOUT = 0 mA; Note 3 | 3 | ||
| Minimum input voltage after start-up | VIN | 0.35 | V | Note 1 | 3 | ||
| NMOS on-resistance | RDS(ON)N | 0.6 | VIN = 3.3V, ISW = 100 mA | 3 | |||
| PMOS on-resistance | RDS(ON)P | 0.9 | VIN = 3.3V, ISW = 100 mA | 3 | |||
| Maximum duty cycle | DCMAX | 90 | % | 4 | |||
| Line regulation | 0.01 | %/V | VIN = 1.5V to 3V; IOUT = 25 mA | 4 | |||
| Load regulation | 0.01 | % | IOUT = 25 mA to 50 mA; VIN = 1.5V | 4 | |||
| EN input leakage current | IENLK | 0.005 | µA | VEN = 5V | 4 | ||
| Soft-start time | tSS | 750 | µS | EN low to high, VOUT reaches 90%; Note 4 | 4 | ||
| Thermal shutdown die temperature | TSD | 150 | °C | 4 | |||
| Die temperature hysteresis | TSDHYS | 10 | °C | 4 | |||
| Thermal resistance, junction to ambient | θJA | 192 | °C/W | EIA/JESD51-3 standard | 4 |
CAD (KiCad official)
- Symbol:
MCP1624T-I - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
mcp1624t-i-etched.step/mcp1624t-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp1624t-i.step/mcp1624t-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (28 pp, sha256
fe27dcd693e4fe6c, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).