component
MCP14E4-E
Public Made by Adomby adom
Microchip Tech Pre-ordered MCUs, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MCP14E4-E
Microchip Tech · Pre-ordered MCUs · PDIP-8
MCP14E4-E from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENB_A | input | Active-high enable for Output A, internally pulled up to VDD and may be left floating; pulling it below VEN_L turns Output A off regardless of the IN A state. |
| 2 | IN A | input | Input A, a high-impedance TTL/CMOS-compatible input (2.4V to 18V) with hysteresis, noninverting for the MCP14E4. |
| 3 | GND | power_in | Ground return pin; it needs a low-impedance connection to the bias supply return because high peak currents flow out of it when the capacitive load is discharged. |
| 4 | IN B | input | Input B, a high-impedance TTL/CMOS-compatible input (2.4V to 18V) with hysteresis, noninverting for the MCP14E4. |
| 5 | OUT B | output | Output B, a CMOS push-pull output that sources and sinks 4.0A peak (VDD = 18V) and has a 1.5A reverse latch-up rating. |
| 6 | VDD | power_in | Bias supply input with a 4.5V to 18V range, which must be decoupled to ground with a local ceramic capacitor. |
| 7 | OUT A | output | Output A, a CMOS push-pull output that sources and sinks 4.0A peak (VDD = 18V) and has a 1.5A reverse latch-up rating. |
| 8 | ENB_B | input | Active-high enable for Output B, internally pulled up to VDD and may be left floating; pulling it below VEN_L turns Output B off regardless of the IN B state. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute max) | 20 | V | 3 | ||||
| Input Current (VIN>VDD) | 50 | mA | VIN>VDD | 3 | |||
| Supply Voltage | VDD | 4.5 | 18 | V | 4 | ||
| Specified Temperature Range | TA | -40 | 125 | °C | 6 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 6 | |||
| Storage Temperature Range | TA | -65 | 150 | °C | 6 | ||
| Thermal Resistance, 8L-PDIP | θJA | 89.3 | °C/W | 6 | |||
| Logic 1 High Input Voltage | VIH | 2.4 | 1.5 | V | TA = +25°C | 3 | |
| Logic 0 Low Input Voltage | VIL | 1.3 | 0.8 | V | TA = +25°C | 3 | |
| Input Current | IIN | -1 | 1 | µA | 0V ≤ VIN ≤ VDD, TA = +25°C | 3 | |
| Input Voltage | VIN | -5 | V | TA = +25°C | 3 | ||
| Low Output Voltage | VOL | 0.025 | V | DC Test, TA = +25°C | 3 | ||
| Output Resistance, High | ROH | 2.5 | 3.5 | Ω | IOUT = 10 mA, VDD = 18V, TA = +25°C | 3 | |
| Output Resistance, Low | ROL | 2.5 | 3 | Ω | IOUT = 10 mA, VDD = 18V, TA = +25°C | 3 | |
| Peak Output Current | IPK | 4 | A | VDD = 18V (Note 2) | 3 | ||
| Rise Time | tR | 15 | 30 | ns | CL = 2200 pF, TA = +25°C | 3 | |
| Fall Time | tF | 18 | 30 | ns | CL = 2200 pF, TA = +25°C | 3 | |
| Propagation Delay Time | tD1 | 46 | 55 | ns | TA = +25°C | 3 | |
| Propagation Delay Time | tD2 | 50 | 55 | ns | TA = +25°C | 3 | |
| Enable High-Level Input Voltage | VEN_H | 1.6 | 1.9 | 2.9 | V | VDD = 12V, LO to HI Transition, TA = +25°C | 3 |
| Enable Low-Level Input Voltage | VEN_L | 1.3 | 2.2 | 2.4 | V | VDD = 12V, HI to LO Transition, TA = +25°C | 3 |
| Enable Hysteresis | VHYST | 0.1 | 0.3 | 0.6 | V | TA = +25°C | 3 |
| Enable Leakage Current | IENBL | 40 | 85 | 115 | µA | VDD = 12V, ENB_A = ENB_B = GND, TA = +25°C | 3 |
| Supply Current | IDD | 1.6 | 2 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = High, TA = +25°C | 4 | |
| Supply Current | IDD | 0.6 | 0.9 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = High, TA = +25°C | 4 | |
| Supply Current | IDD | 1.2 | 1.4 | mA | VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = High, TA = +25°C | 4 | |
| Supply Current | IDD | 1.4 | 1.8 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = Low, TA = +25°C | 4 | |
| Supply Current | IDD | 0.55 | 0.75 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = Low, TA = +25°C | 4 | |
| Supply Current | IDD | 1 | 1.2 | mA | VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = Low, TA = +25°C | 4 | |
| Logic 1 High Input Voltage (over temp) | VIH | 2.4 | V | Operating temperature range | 5 | ||
| Logic 0 Low Input Voltage (over temp) | VIL | 0.8 | V | Operating temperature range | 5 | ||
| Input Current (over temp) | IIN | -10 | 10 | µA | 0V ≤ VIN ≤ VDD, operating temperature range | 5 | |
| Low Output Voltage (over temp) | VOL | 0.025 | V | DC TEST, operating temperature range | 5 | ||
| Output Resistance, High (over temp) | ROH | 3 | 6 | Ω | IOUT = 10 mA, VDD = 18V, operating temperature range | 5 | |
| Output Resistance, Low (over temp) | ROL | 3 | 5 | Ω | IOUT = 10 mA, VDD = 18V, operating temperature range | 5 | |
| Rise Time (over temp) | tR | 25 | 40 | ns | CL = 2200 pF, operating temperature range | 5 | |
| Fall Time (over temp) | tF | 28 | 40 | ns | CL = 2200 pF, operating temperature range | 5 | |
| Delay Time (over temp) | tD1 | 50 | 70 | ns | Operating temperature range | 5 | |
| Enable High-Level Input Voltage (over temp) | VEN_H | 1.6 | 2.2 | 2.9 | V | VDD = 12V, LO to HI Transition | 5 |
| Enable Low-Level Input Voltage (over temp) | VEN_L | 1.3 | 1.8 | 2.4 | V | VDD = 12V, HI to LO Transition | 5 |
| Enable Leakage Current (over temp) | IENBL | 40 | 87 | 115 | µA | VDD = 12V, ENB_A = ENB_B = GND | 5 |
| Supply Current (over temp) | IDD | 2 | 3 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = High | 5 | |
| Supply Current (over temp) | IDD | 0.8 | 1.1 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = High | 5 | |
| Supply Current (over temp) | IDD | 1.8 | 2.8 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = Low | 5 | |
| Supply Current (over temp) | IDD | 0.6 | 0.8 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = Low | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN), Narrow, 3.90 mm Body [SOIC] Notes: | 18 |
CAD (KiCad official)
- Symbol:
MCP14E4-E - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
mcp14e4-e-etched.step/mcp14e4-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp14e4-e.step/mcp14e4-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (26 pp, sha256
0dce349db3a31868, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP14E4-E
**Microchip Tech** · Pre-ordered MCUs · PDIP-8
MCP14E4-E from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENB_A | input | Active-high enable for Output A, internally pulled up to VDD and may be left floating; pulling it below VEN_L turns Output A off regardless of the IN A state. |
| 2 | IN A | input | Input A, a high-impedance TTL/CMOS-compatible input (2.4V to 18V) with hysteresis, noninverting for the MCP14E4. |
| 3 | GND | power_in | Ground return pin; it needs a low-impedance connection to the bias supply return because high peak currents flow out of it when the capacitive load is discharged. |
| 4 | IN B | input | Input B, a high-impedance TTL/CMOS-compatible input (2.4V to 18V) with hysteresis, noninverting for the MCP14E4. |
| 5 | OUT B | output | Output B, a CMOS push-pull output that sources and sinks 4.0A peak (VDD = 18V) and has a 1.5A reverse latch-up rating. |
| 6 | VDD | power_in | Bias supply input with a 4.5V to 18V range, which must be decoupled to ground with a local ceramic capacitor. |
| 7 | OUT A | output | Output A, a CMOS push-pull output that sources and sinks 4.0A peak (VDD = 18V) and has a 1.5A reverse latch-up rating. |
| 8 | ENB_B | input | Active-high enable for Output B, internally pulled up to VDD and may be left floating; pulling it below VEN_L turns Output B off regardless of the IN B state. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute max) | | | | 20 | V | | 3 |
| Input Current (VIN>VDD) | | | | 50 | mA | VIN>VDD | 3 |
| Supply Voltage | VDD | 4.5 | | 18 | V | | 4 |
| Specified Temperature Range | TA | -40 | | 125 | °C | | 6 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 6 |
| Storage Temperature Range | TA | -65 | | 150 | °C | | 6 |
| Thermal Resistance, 8L-PDIP | θJA | | 89.3 | | °C/W | | 6 |
| Logic 1 High Input Voltage | VIH | 2.4 | 1.5 | | V | TA = +25°C | 3 |
| Logic 0 Low Input Voltage | VIL | | 1.3 | 0.8 | V | TA = +25°C | 3 |
| Input Current | IIN | -1 | | 1 | µA | 0V ≤ VIN ≤ VDD, TA = +25°C | 3 |
| Input Voltage | VIN | -5 | | | V | TA = +25°C | 3 |
| Low Output Voltage | VOL | | | 0.025 | V | DC Test, TA = +25°C | 3 |
| Output Resistance, High | ROH | | 2.5 | 3.5 | Ω | IOUT = 10 mA, VDD = 18V, TA = +25°C | 3 |
| Output Resistance, Low | ROL | | 2.5 | 3 | Ω | IOUT = 10 mA, VDD = 18V, TA = +25°C | 3 |
| Peak Output Current | IPK | | 4 | | A | VDD = 18V (Note 2) | 3 |
| Rise Time | tR | | 15 | 30 | ns | CL = 2200 pF, TA = +25°C | 3 |
| Fall Time | tF | | 18 | 30 | ns | CL = 2200 pF, TA = +25°C | 3 |
| Propagation Delay Time | tD1 | | 46 | 55 | ns | TA = +25°C | 3 |
| Propagation Delay Time | tD2 | | 50 | 55 | ns | TA = +25°C | 3 |
| Enable High-Level Input Voltage | VEN_H | 1.6 | 1.9 | 2.9 | V | VDD = 12V, LO to HI Transition, TA = +25°C | 3 |
| Enable Low-Level Input Voltage | VEN_L | 1.3 | 2.2 | 2.4 | V | VDD = 12V, HI to LO Transition, TA = +25°C | 3 |
| Enable Hysteresis | VHYST | 0.1 | 0.3 | 0.6 | V | TA = +25°C | 3 |
| Enable Leakage Current | IENBL | 40 | 85 | 115 | µA | VDD = 12V, ENB_A = ENB_B = GND, TA = +25°C | 3 |
| Supply Current | IDD | | 1.6 | 2 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = High, TA = +25°C | 4 |
| Supply Current | IDD | | 0.6 | 0.9 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = High, TA = +25°C | 4 |
| Supply Current | IDD | | 1.2 | 1.4 | mA | VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = High, TA = +25°C | 4 |
| Supply Current | IDD | | 1.4 | 1.8 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = Low, TA = +25°C | 4 |
| Supply Current | IDD | | 0.55 | 0.75 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = Low, TA = +25°C | 4 |
| Supply Current | IDD | | 1 | 1.2 | mA | VIN_A = 3V, VIN_B = 0V, ENB_A = ENB_B = Low, TA = +25°C | 4 |
| Logic 1 High Input Voltage (over temp) | VIH | 2.4 | | | V | Operating temperature range | 5 |
| Logic 0 Low Input Voltage (over temp) | VIL | | | 0.8 | V | Operating temperature range | 5 |
| Input Current (over temp) | IIN | -10 | | 10 | µA | 0V ≤ VIN ≤ VDD, operating temperature range | 5 |
| Low Output Voltage (over temp) | VOL | | | 0.025 | V | DC TEST, operating temperature range | 5 |
| Output Resistance, High (over temp) | ROH | | 3 | 6 | Ω | IOUT = 10 mA, VDD = 18V, operating temperature range | 5 |
| Output Resistance, Low (over temp) | ROL | | 3 | 5 | Ω | IOUT = 10 mA, VDD = 18V, operating temperature range | 5 |
| Rise Time (over temp) | tR | | 25 | 40 | ns | CL = 2200 pF, operating temperature range | 5 |
| Fall Time (over temp) | tF | | 28 | 40 | ns | CL = 2200 pF, operating temperature range | 5 |
| Delay Time (over temp) | tD1 | | 50 | 70 | ns | Operating temperature range | 5 |
| Enable High-Level Input Voltage (over temp) | VEN_H | 1.6 | 2.2 | 2.9 | V | VDD = 12V, LO to HI Transition | 5 |
| Enable Low-Level Input Voltage (over temp) | VEN_L | 1.3 | 1.8 | 2.4 | V | VDD = 12V, HI to LO Transition | 5 |
| Enable Leakage Current (over temp) | IENBL | 40 | 87 | 115 | µA | VDD = 12V, ENB_A = ENB_B = GND | 5 |
| Supply Current (over temp) | IDD | | 2 | 3 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = High | 5 |
| Supply Current (over temp) | IDD | | 0.8 | 1.1 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = High | 5 |
| Supply Current (over temp) | IDD | | 1.8 | 2.8 | mA | VIN_A = 3V, VIN_B = 3V, ENB_A = ENB_B = Low | 5 |
| Supply Current (over temp) | IDD | | 0.6 | 0.8 | mA | VIN_A = 0V, VIN_B = 0V, ENB_A = ENB_B = Low | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | 8-Lead Plastic Small Outline (SN), Narrow, 3.90 mm Body [SOIC] Notes: | 18 |
## CAD (KiCad official)
- Symbol: `MCP14E4-E`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files: `mcp14e4-e-etched.step` / `mcp14e4-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp14e4-e.step` / `mcp14e4-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp14e4-e-datasheet.pdf) (26 pp, sha256 `0dce349db3a31868`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp14e4-e-datasheet.pdf)