component
MCP14A0602-E
Public Made by Adomby adom
Microchip Tech Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MCP14A0602-E
Microchip Tech · Gate Drive ICs · SOIC-8
MCP14A0602-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Bias supply input for the MOSFET driver with a voltage range of 4.5V to 18V, which must be decoupled to ground with a local capacitor. |
| 2 | IN | input | High-impedance control input with low threshold levels and hysteresis, allowing it to be driven from slow rising and falling signals and providing noise immunity. |
| 3 | EN | input | High-impedance active-high enable with low threshold levels; driving it below threshold pulls OUT/OUT low regardless of IN, and an internal pull-up lets it float for standard operation. |
| 4 | GND | power_in | Power ground and device return for the input and output stages, requiring a low-impedance connection to the bias supply source return. |
| 5 | GND | power_in | Power ground and device return for the input and output stages, requiring a low-impedance connection to the bias supply source return. |
| 6 | OUT/OUT | output | CMOS push-pull output capable of sourcing and sinking 6.0A of peak current at VDD = 18V, with a reverse current latch-up rating of 500 mA. |
| 7 | OUT/OUT | output | CMOS push-pull output capable of sourcing and sinking 6.0A of peak current at VDD = 18V, with a reverse current latch-up rating of 500 mA. |
| 8 | VDD | power_in | Bias supply input for the MOSFET driver with a voltage range of 4.5V to 18V, which must be decoupled to ground with a local capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1 High Input Voltage | VIH | 2 | 1.6 | V | 3 | ||
| Logic 0 Low Input Voltage | VIL | 1.2 | 0.8 | V | 3 | ||
| Input Current | IIN | -1 | 1 | µA | 0V VIN VDD | 3 | |
| Logic 1 High Enable Voltage | VEH | 2 | 1.6 | V | 3 | ||
| Logic 0 Low Enable Voltage | VEL | 1.2 | 0.8 | V | 3 | ||
| Propagation Delay tD3 | tD3 | 22 | 29 | ns | VDD = 18V, VEN = 5V, see Figure 4-3, (Note 1) | 3 | |
| Propagation Delay tD4 | tD4 | 22 | 29 | ns | VDD = 18V, VEN = 5V, see Figure 4-3, (Note 1) | 3 | |
| Low Output Voltage | VOL | 0.025 | V | IOUT = 0A | 3 | ||
| Output Resistance, High | ROH | 1.2 | 2.3 | Ω | IOUT = 10 mA, VDD = 18V | 3 | |
| Output Resistance, Low | ROL | 0.9 | 2 | Ω | IOUT = 10 mA, VDD = 18V | 3 | |
| Latch-Up Protection Withstand Reverse Current | IREV | 0.5 | A | Duty cycle 2%, t 300 µs (Note 1) | 3 | ||
| Rise Time | tR | 10 | 15 | ns | VDD = 18V, CL = 2500 pF, see Figure 4-1, Figure 4-2 | 3 | |
| Fall Time | tF | 10 | 15 | ns | VDD = 18V, CL = 2500 pF, see Figure 4-1, Figure 4-2 | 3 | |
| Delay Time tD1 | tD1 | 22 | 29 | ns | VDD = 18V, VIN = 5V, see Figure 4-1 and Figure 4-2 | 4 | |
| Delay Time tD2 | tD2 | 22 | 29 | ns | VDD = 18V, VIN = 5V, see Figure 4-1 and Figure 4-2 | 4 | |
| Supply Voltage | VDD | 4.5 | 18 | V | 4 | ||
| Power Supply Current | IDD | 330 | 560 | µA | VIN = 3V, VEN = 3V | 4 | |
| Power Supply Current | IDD | 360 | 580 | µA | VIN = 0V, VEN = 3V | 4 | |
| Power Supply Current | IDD | 375 | 600 | µA | VIN = 0V, VEN = 0V | 4 | |
| Logic 1 High Input Voltage (over temperature) | VIH | 2 | 1.6 | V | 4 | ||
| Logic 0 Low Input Voltage (over temperature) | VIL | 1.2 | 0.8 | V | 4 | ||
| Input Current (over temperature) | IIN | -10 | 10 | µA | 0V VIN VDD | 4 | |
| Logic 1 High Enable Voltage (over temperature) | VEH | 2 | 1.6 | V | 4 | ||
| Logic 0 Low Enable Voltage (over temperature) | VEL | 1.2 | 0.8 | V | 4 | ||
| Propagation Delay tD3 (over temperature) | tD3 | 26 | 33 | ns | VDD = 18V, VEN = 5V, TA = +125°C, see Figure 4-3 | 4 | |
| Propagation Delay tD4 (over temperature) | tD4 | 26 | 33 | ns | VDD = 18V, VEN = 5V, TA = +125°C, see Figure 4-3 | 4 | |
| Low Output Voltage (over temperature) | VOL | 0.025 | V | DC Test | 4 | ||
| Output Resistance, High (over temperature) | ROH | 2.9 | Ω | IOUT = 10 mA, VDD = 18V | 4 | ||
| Output Resistance, Low (over temperature) | ROL | 2.6 | Ω | IOUT = 10 mA, VDD = 18V | 4 | ||
| Rise Time at 125°C | tR | 12 | 17 | ns | VDD = 18V, CL = 2500 pF, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 | |
| Fall Time at 125°C | tF | 12 | 17 | ns | VDD = 18V, CL = 2500 pF, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 | |
| Delay Time tD1 at 125°C | tD1 | 26 | 33 | ns | VDD = 18V, VIN = 5V, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 | |
| Delay Time tD2 at 125°C | tD2 | 26 | 33 | ns | VDD = 18V, VIN = 5V, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 | |
| Supply Voltage (125°C table) | VDD | 4.5 | 18 | V | 5 | ||
| Power Supply Current at 125°C | IDD | 760 | uA | VIN = 3V, VEN = 3V | 5 | ||
| Power Supply Current at 125°C | IDD | 780 | uA | VIN = 0V, VEN = 3V | 5 | ||
| Power Supply Current at 125°C | IDD | 800 | uA | VIN = 0V, VEN = 0V | 5 | ||
| Specified Temperature Range | TA | -40 | 125 | °C | 5 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 5 | |||
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Supply Voltage (absolute maximum) | VDD | 20 | V | 3 | |||
| Package Power Dissipation 8L SOIC | PD | 1 | W | TA = +50°C | 3 | ||
| ESD Protection on all pins (HBM) | 2 | kV | HBM | 3 | |||
| Peak Output Current | IPK | 6 | A | VDD = 18V (Note 1) | 3 | ||
| Enable Pin Pull-Up Resistance | RENBL | 1.8 | MΩ | VDD = 18V, ENB = GND | 3 | ||
| Enable Input Current | IEN | 10 | µA | VDD = 18V, ENB = GND | 3 | ||
| Enable Input Current (over temperature) | IEN | 12 | µA | VDD = 18V, ENB = GND | 4 | ||
| Junction-to-Ambient Thermal Resistance, 8LD SOIC | θJA | 99.8 | °C/W | Note 1 | 5 | ||
| Junction-to-Top Characterization Parameter, 8LD SOIC | ΨJT | 5.9 | °C/W | Note 1 | 5 | ||
| Junction-to-Board Characterization Parameter, 8LD SOIC | ΨJB | 64.8 | °C/W | Note 1 | 5 | ||
| Input Voltage Hysteresis | VHYST(IN) | 0.4 | V | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | SN = 8-Lead Plastic Small Outline - Narrow, 3.90 mm Body (SOIC) | 27 |
CAD (KiCad official)
- Symbol:
MCP14A0602-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp14a0602-e-etched.step/mcp14a0602-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp14a0602-e.step/mcp14a0602-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (30 pp, sha256
76dae55e05e4a3b2, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MCP14A0602-E
**Microchip Tech** · Gate Drive ICs · SOIC-8
MCP14A0602-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Bias supply input for the MOSFET driver with a voltage range of 4.5V to 18V, which must be decoupled to ground with a local capacitor. |
| 2 | IN | input | High-impedance control input with low threshold levels and hysteresis, allowing it to be driven from slow rising and falling signals and providing noise immunity. |
| 3 | EN | input | High-impedance active-high enable with low threshold levels; driving it below threshold pulls OUT/OUT low regardless of IN, and an internal pull-up lets it float for standard operation. |
| 4 | GND | power_in | Power ground and device return for the input and output stages, requiring a low-impedance connection to the bias supply source return. |
| 5 | GND | power_in | Power ground and device return for the input and output stages, requiring a low-impedance connection to the bias supply source return. |
| 6 | OUT/OUT | output | CMOS push-pull output capable of sourcing and sinking 6.0A of peak current at VDD = 18V, with a reverse current latch-up rating of 500 mA. |
| 7 | OUT/OUT | output | CMOS push-pull output capable of sourcing and sinking 6.0A of peak current at VDD = 18V, with a reverse current latch-up rating of 500 mA. |
| 8 | VDD | power_in | Bias supply input for the MOSFET driver with a voltage range of 4.5V to 18V, which must be decoupled to ground with a local capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1 High Input Voltage | VIH | 2 | 1.6 | | V | | 3 |
| Logic 0 Low Input Voltage | VIL | | 1.2 | 0.8 | V | | 3 |
| Input Current | IIN | -1 | | 1 | µA | 0V VIN VDD | 3 |
| Logic 1 High Enable Voltage | VEH | 2 | 1.6 | | V | | 3 |
| Logic 0 Low Enable Voltage | VEL | | 1.2 | 0.8 | V | | 3 |
| Propagation Delay tD3 | tD3 | | 22 | 29 | ns | VDD = 18V, VEN = 5V, see Figure 4-3, (Note 1) | 3 |
| Propagation Delay tD4 | tD4 | | 22 | 29 | ns | VDD = 18V, VEN = 5V, see Figure 4-3, (Note 1) | 3 |
| Low Output Voltage | VOL | | | 0.025 | V | IOUT = 0A | 3 |
| Output Resistance, High | ROH | | 1.2 | 2.3 | Ω | IOUT = 10 mA, VDD = 18V | 3 |
| Output Resistance, Low | ROL | | 0.9 | 2 | Ω | IOUT = 10 mA, VDD = 18V | 3 |
| Latch-Up Protection Withstand Reverse Current | IREV | 0.5 | | | A | Duty cycle 2%, t 300 µs (Note 1) | 3 |
| Rise Time | tR | | 10 | 15 | ns | VDD = 18V, CL = 2500 pF, see Figure 4-1, Figure 4-2 | 3 |
| Fall Time | tF | | 10 | 15 | ns | VDD = 18V, CL = 2500 pF, see Figure 4-1, Figure 4-2 | 3 |
| Delay Time tD1 | tD1 | | 22 | 29 | ns | VDD = 18V, VIN = 5V, see Figure 4-1 and Figure 4-2 | 4 |
| Delay Time tD2 | tD2 | | 22 | 29 | ns | VDD = 18V, VIN = 5V, see Figure 4-1 and Figure 4-2 | 4 |
| Supply Voltage | VDD | 4.5 | | 18 | V | | 4 |
| Power Supply Current | IDD | | 330 | 560 | µA | VIN = 3V, VEN = 3V | 4 |
| Power Supply Current | IDD | | 360 | 580 | µA | VIN = 0V, VEN = 3V | 4 |
| Power Supply Current | IDD | | 375 | 600 | µA | VIN = 0V, VEN = 0V | 4 |
| Logic 1 High Input Voltage (over temperature) | VIH | 2 | 1.6 | | V | | 4 |
| Logic 0 Low Input Voltage (over temperature) | VIL | | 1.2 | 0.8 | V | | 4 |
| Input Current (over temperature) | IIN | -10 | | 10 | µA | 0V VIN VDD | 4 |
| Logic 1 High Enable Voltage (over temperature) | VEH | 2 | 1.6 | | V | | 4 |
| Logic 0 Low Enable Voltage (over temperature) | VEL | | 1.2 | 0.8 | V | | 4 |
| Propagation Delay tD3 (over temperature) | tD3 | | 26 | 33 | ns | VDD = 18V, VEN = 5V, TA = +125°C, see Figure 4-3 | 4 |
| Propagation Delay tD4 (over temperature) | tD4 | | 26 | 33 | ns | VDD = 18V, VEN = 5V, TA = +125°C, see Figure 4-3 | 4 |
| Low Output Voltage (over temperature) | VOL | | | 0.025 | V | DC Test | 4 |
| Output Resistance, High (over temperature) | ROH | | | 2.9 | Ω | IOUT = 10 mA, VDD = 18V | 4 |
| Output Resistance, Low (over temperature) | ROL | | | 2.6 | Ω | IOUT = 10 mA, VDD = 18V | 4 |
| Rise Time at 125°C | tR | | 12 | 17 | ns | VDD = 18V, CL = 2500 pF, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 |
| Fall Time at 125°C | tF | | 12 | 17 | ns | VDD = 18V, CL = 2500 pF, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 |
| Delay Time tD1 at 125°C | tD1 | | 26 | 33 | ns | VDD = 18V, VIN = 5V, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 |
| Delay Time tD2 at 125°C | tD2 | | 26 | 33 | ns | VDD = 18V, VIN = 5V, TA = +125°C, see Figure 4-1, Figure 4-2 | 5 |
| Supply Voltage (125°C table) | VDD | 4.5 | | 18 | V | | 5 |
| Power Supply Current at 125°C | IDD | | | 760 | uA | VIN = 3V, VEN = 3V | 5 |
| Power Supply Current at 125°C | IDD | | | 780 | uA | VIN = 0V, VEN = 3V | 5 |
| Power Supply Current at 125°C | IDD | | | 800 | uA | VIN = 0V, VEN = 0V | 5 |
| Specified Temperature Range | TA | -40 | | 125 | °C | | 5 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 5 |
| Storage Temperature Range | TA | -65 | | 150 | °C | | 5 |
| Supply Voltage (absolute maximum) | VDD | | | 20 | V | | 3 |
| Package Power Dissipation 8L SOIC | PD | | | 1 | W | TA = +50°C | 3 |
| ESD Protection on all pins (HBM) | | | | 2 | kV | HBM | 3 |
| Peak Output Current | IPK | | 6 | | A | VDD = 18V (Note 1) | 3 |
| Enable Pin Pull-Up Resistance | RENBL | | 1.8 | | MΩ | VDD = 18V, ENB = GND | 3 |
| Enable Input Current | IEN | | 10 | | µA | VDD = 18V, ENB = GND | 3 |
| Enable Input Current (over temperature) | IEN | | 12 | | µA | VDD = 18V, ENB = GND | 4 |
| Junction-to-Ambient Thermal Resistance, 8LD SOIC | θJA | | 99.8 | | °C/W | Note 1 | 5 |
| Junction-to-Top Characterization Parameter, 8LD SOIC | ΨJT | | 5.9 | | °C/W | Note 1 | 5 |
| Junction-to-Board Characterization Parameter, 8LD SOIC | ΨJB | | 64.8 | | °C/W | Note 1 | 5 |
| Input Voltage Hysteresis | VHYST(IN) | | 0.4 | | V | | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | SN = 8-Lead Plastic Small Outline - Narrow, 3.90 mm Body (SOIC) | 27 |
## CAD (KiCad official)
- Symbol: `MCP14A0602-E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mcp14a0602-e-etched.step` / `mcp14a0602-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mcp14a0602-e.step` / `mcp14a0602-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/mcp14a0602-e-datasheet.pdf) (30 pp, sha256 `76dae55e05e4a3b2`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mcp14a0602-e-datasheet.pdf)