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MC9S08MP16VLF

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NXP Semicon Pre-ordered MCUs, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC9S08MP16VLF

NXP Semicon · Pre-ordered MCUs · LQFP-48(7x7)

MC9S08MP16VLF from NXP Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PTC4/KBI2P4/FTM2CH4 bidirectional Port C bit 4 GPIO with alternate functions KBI2 input 4 and FTM2 channel 4.
2 PTC5/KBI2P5/FTM2CH5 bidirectional Port C bit 5 GPIO with alternate functions KBI2 input 5 and FTM2 channel 5.
3 PTC6/KBI2P6/FTM2FAULT bidirectional Port C bit 6 GPIO with alternate functions KBI2 input 6 and FTM2 fault input.
4 PTC7/KBI2P7/TCLK bidirectional Port C bit 7 GPIO with KBI2 input 7 and TCLK external clock input (default TCLK location, repositionable via TCLKPS in SOPT2).
5 PTD0/KBI3P0/SDA bidirectional Port D bit 0 GPIO with KBI3 input 0 and IIC SDA (default reset IIC location, repositionable via IICPS in SOPT2).
6 PTD1/KBI3P1/SCL bidirectional Port D bit 1 GPIO with KBI3 input 1 and IIC SCL (default reset IIC location, repositionable via IICPS in SOPT2).
7 PTD2/KBI3P2/PDB1OUT bidirectional Port D bit 2 GPIO with KBI3 input 2 and PDB1 output.
8 PTD3/KBI3P3/FTM1FAULT bidirectional Port D bit 3 GPIO with KBI3 input 3 and FTM1 fault input.
9 VSS1 power_in Digital ground supply pin 1.
10 VDD1 power_in Digital positive supply pin 1 (device operates at 2.7 V to 5.5 V).
11 PTA0/SDA/TxD bidirectional Port A bit 0 GPIO with IIC SDA and SCI transmit data.
12 PTA1/SCL/RxD bidirectional Port A bit 1 GPIO with IIC SCL and SCI receive data.
13 PTA2/SDA/FTM1CH0 bidirectional Port A bit 2 GPIO with IIC SDA and FTM1 channel 0.
14 PTA3/SCL/FTM1CH1 bidirectional Port A bit 3 GPIO with IIC SCL and FTM1 channel 1.
15 PTD4/KBI3P4/PDB2OUT bidirectional Port D bit 4 GPIO with KBI3 input 4 and PDB2 output.
16 PTD5/KBI3P5/CMP1OUT bidirectional Port D bit 5 GPIO with KBI3 input 5 and HSCMP1 output.
17 PTD6/KBI3P6/CMP2OUT bidirectional Port D bit 6 GPIO with KBI3 input 6 and HSCMP2 output (default CMP2OUT location, repositionable via CMP2OPS in SOPT2).
18 PTD7/KBI3P7/CMP3OUT bidirectional Port D bit 7 GPIO with KBI3 input 7 and HSCMP3 output (default CMP3OUT location, repositionable via CMP3OPS in SOPT2).
19 PTF1/RESET bidirectional Port F bit 1 or active-low RESET; open drain with an always-enabled internal pullup, no clamp diode to VDD and must not be driven above VDD.
20 PTF2 bidirectional Port F bit 2 general-purpose pin with no alternate function listed.
21 PTA4/TCLK/SDA/SS bidirectional Port A bit 4 GPIO with TCLK input, IIC SDA and SPI slave select.
22 PTA5/SCL/MISO bidirectional Port A bit 5 GPIO with IIC SCL and SPI MISO.
23 PTA6/MOSI bidirectional Port A bit 6 GPIO with SPI MOSI.
24 PTA7/SPSCK bidirectional Port A bit 7 GPIO with SPI clock SPSCK.
25 PTE0/ADP8 bidirectional Port E bit 0 GPIO with ADC input channel 8.
26 PTE1/ADP9 bidirectional Port E bit 1 GPIO with ADC input channel 9.
27 PTE2/ADP10 bidirectional Port E bit 2 GPIO with ADC input channel 10.
28 PTB0/KBI1P0/ADP0/CIN1 bidirectional Port B bit 0 GPIO with KBI1 input 0, ADC channel 0 and HSCMP1 input CIN1.
29 PTB1/KBI1P1/ADP1/C2IN2 bidirectional Port B bit 1 GPIO with KBI1 input 1, ADC channel 1 and HSCMP2 input C2IN2.
30 PTB2/KBI1P2/ADP2/C1IN2/PGA+ bidirectional Port B bit 2 GPIO with KBI1 input 2, ADC channel 2, HSCMP1 input C1IN2 and PGA positive input.
31 PTB3/KBI1P3/ADP3/C3IN2/PGA- bidirectional Port B bit 3 GPIO with KBI1 input 3, ADC channel 3, HSCMP3 input C3IN2 and PGA negative input.
32 VDDA/VREFH power_in Analog positive supply and ADC/DAC high voltage reference.
33 VSSA/VREFL power_in Analog ground and ADC/DAC low voltage reference.
34 PTE3/ADP11/C1IN3 bidirectional Port E bit 3 GPIO with ADC channel 11 and HSCMP1 input C1IN3.
35 PTE4/ADP12/C1IN4 bidirectional Port E bit 4 GPIO with ADC channel 12 and HSCMP1 input C1IN4.
36 PTB4/KBI1P4/ADP4/C2IN3 bidirectional Port B bit 4 GPIO with KBI1 input 4, ADC channel 4 and HSCMP2 input C2IN3.
37 PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4 bidirectional Port B bit 5 GPIO with KBI1 input 5, HSCMP2 output (alternate location), ADC channel 5 and HSCMP2 input C2IN4.
38 PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3 bidirectional Port B bit 6 GPIO with KBI1 input 6, HSCMP3 output (alternate location), ADC channel 6 and HSCMP3 input C3IN3.
39 PTB7/KBI1P7/ADP7/C3IN4 bidirectional Port B bit 7 GPIO with KBI1 input 7, ADC channel 7 and HSCMP3 input C3IN4.
40 PTE5/XTAL bidirectional Port E bit 5 GPIO or oscillator (XOSC) crystal output pin XTAL.
41 PTE6/EXTAL bidirectional Port E bit 6 GPIO or oscillator (XOSC) external clock/crystal input pin EXTAL.
42 VSS2 power_in Digital ground supply pin 2.
43 VDD2 power_in Digital positive supply pin 2.
44 PTF0/BKGD/MS bidirectional Port F bit 0 or single-wire background debug pin BKGD/MS, bidirectional when configured as BKGD.
45 PTC0/KBI2P0/FTM2CH0 bidirectional Port C bit 0 GPIO with KBI2 input 0 and FTM2 channel 0.
46 PTC1/KBI2P1/FTM2CH1 bidirectional Port C bit 1 GPIO with KBI2 input 1 and FTM2 channel 1.
47 PTC2/KBI2P2/FTM2CH2 bidirectional Port C bit 2 GPIO with KBI2 input 2 and FTM2 channel 2.
48 PTC3/KBI2P3/FTM2CH3 bidirectional Port C bit 3 GPIO with KBI2 input 3 and FTM2 channel 3.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage VDD 2.7 5.5 V 11
Operating temperature range (packaged) TA -40 105 C Consumer & Industrial 10
Supply voltage VDD -0.3 5.8 V 9
Maximum current into VDD IDD 120 mA 9
Digital input voltage VIn -0.3 5.8 V -0.3 to VDD + 0.3 V as printed 9
Instantaneous maximum current single pin ID 25 mA applies to all port pins 9
Storage temperature range Tstg -55 150 C 9
Maximum junction temperature TJ 115 C Consumer & Industrial 10
Thermal resistance 48-pin LQFP, single-layer board θJA 80 C/W Junction-to-ambient natural convection 10
Thermal resistance 48-pin LQFP, four-layer board θJA 56 C/W Junction-to-ambient natural convection 10
Human body model ESD VHBM 2000 V 11
Charge device model ESD VCDM 500 V 11
Latch-up current ILAT 100 mA TA = 125C 11
Analog supply voltage delta to VDD VDDA 0 100 mV VDD - VDDA 11
Analog ground voltage delta to VSS VSSA 0 100 mV VSS - VSSA 11
Output high voltage low-drive VOH 0.8 V 5 V, ILoad = -2 mA; min is VDD - 0.8 12
Output high voltage high-drive VOH 1.5 V 5 V, ILoad = -20 mA; min is VDD - 1.5 12
Max total IOH for all ports IOHT -100 0 mA VOUT < VDD 12
Output low voltage low-drive VOL 1.5 V 5 V, ILoad = 4 mA 12
Output low voltage high-drive VOL 1.5 V 5 V, ILoad = 20 mA 12
Output low voltage PTF1/RESET VOL 1.5 V 5 V, ILoad = 3.2 mA 12
Max total IOL for all ports IOLT 0 100 mA VOUT > VSS 12
Input high voltage VIH 0.65 V 5V; 0.65 x VDD 12
Input low voltage VIL 0.35 V 5V; 0.35 x VDD 12
Input leakage current IIn 1 A VIn = VDD or VSS 12
Hi-Z leakage current IOZ 1 A VIn = VDD or VSS 12
Pullup/pulldown resistors I/O pins RPU,RPD 17 37 52 k 12
Input capacitance CIn 8 pF all pins 13
RAM retention voltage VRAM 0.6 1 V 13
POR re-arm voltage VPOR 0.9 1.4 2 V 13
Low-voltage detection threshold high range VLVD1 3.9 4 4.1 V VDD falling 13
Low-voltage detection threshold low range VLVD0 2.48 2.56 2.64 V VDD falling 13
Bandgap voltage reference at 25C VBG 1.18 1.202 1.21 V 25C 13
Bandgap voltage reference across temperature VBG 1.17 1.22 V across temperature range 13
Run supply current 4 MHz CPU RIDD 2.16 3 mA CPU 4 MHz, fBus 2 MHz, VDD 5 V 15
Run supply current 16 MHz CPU RIDD 5.26 7.5 mA CPU 16 MHz, fBus 8 MHz, VDD 5 V 15
Run supply current 32 MHz CPU RIDD 9.4 10 mA CPU 32 MHz, fBus 16 MHz, VDD 5 V 16
Run supply current 51.34 MHz CPU RIDD 14.3 30 mA CPU 51.34 MHz, fBus 25.67 MHz, VDD 5 V 16
Stop3 supply current 105C S3IDD 37 90 A VDD 5 V, 105C 16
Stop3 supply current 85C S3IDD 7.5 25 A VDD 5 V, 85C 16
Stop2 supply current 105C S2IDD 30 65 A VDD 5 V, 105C 16
RTC adder to stop2 or stop3 S23IDDRTC 300 500 nA VDD 5 V 16
LVD adder to stop3 S3IDDLVD 110 180 A LVDE = LVDSE = 1, VDD 5 V 17
Oscillator crystal frequency high range fhi 1 16 MHz RANGE = 1, FEE or FBE mode 20
Internal reference frequency factory trimmed fint_t 32.768 kHz VDD = 5 V, 25C, consumer/industrial 21
Internal reference frequency user trimmed fint_t 31.25 39.06 kHz 21
Total deviation of trimmed DCO output frequency over voltage and temperature fdco_t 0.8 2 %fdco 22
ADC supply voltage VDDA 2.7 5.5 V Absolute 23
ADC conversion clock frequency high speed fADCK 0.4 8 MHz ADLPC=0 23
ADC total unadjusted error 12 bit ETUE 3 6.5 LSB 12 bit mode 25
ADC differential non-linearity 12 bit DNL 1.75 3.5 LSB 12 bit mode 25
ADC integral non-linearity 12 bit INL 1.5 4.5 LSB 12 bit mode 25
DAC step size Vstep 0.75 1 1.25 V x Vin/32 26
HSCMP analog input offset voltage VAIO 5 40 mV 26
HSCMP hysteresis VH 3 9 20 mV 26
PGA max gain error EG 1 2 % 27
Bus frequency fBus 0 25.67 MHz -40 to 105 C 27
Internal low power oscillator period tLPO 700 1300 s 27
External reset pulse width textrst 100 ns 27
Flash supply voltage for program/erase Vprog/erase 2.7 5.5 V -40C to 125C 33
Flash program/erase endurance 10000 100000 cycles TL to TH = -40C to +125C; typ at T = 25C 33
Flash data retention tD_ret 15 100 years 33

CAD (KiCad official)

  • Symbol: MC9S08MP16VLF
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: mc9s08mp16vlf-etched.step / mc9s08mp16vlf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc9s08mp16vlf.step / mc9s08mp16vlf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (36 pp, sha256 d1b6e66ec948d4d6, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF