MC79L05ACDR2G
Public Made by Adomby adom
onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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MC79L05ACDR2G
onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
MC79L05ACDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vout | power_out | Regulated negative output voltage, nominally -5.0 V (-4.75 V to -5.25 V over line/load). Output current up to 100 mA (40 mA in SOIC-8 depending on thermal). A 0.1 uF output bypass capacitor is recommended for stability and transient response. |
| 2 | Vin | power_in | Unregulated negative input supply. Nominal operating range -7.0 V to -20 V for the -5 V version (absolute max -30 V). Pins 2, 3, 6, and 7 are all tied together internally as the input node; a 0.33 uF bypass capacitor to ground is recommended close to the pins. |
| 3 | Vin | power_in | Negative input supply (same net as pins 2, 6, 7). Multiple pins share the input node to reduce lead inductance and improve current handling on the SOIC-8 package. |
| 4 | NC | unconnected | No internal connection. Leave floating or tie to a convenient net for PCB routing; not required for operation. |
| 5 | GND | power_in | Common ground reference. Must be shared between input and output. Keep ground return short to avoid loop drops since the regulator has no external sense lead. |
| 6 | Vin | power_in | Negative input supply (same net as pins 2, 3, 7). Multiple Vin pins spread current and thermal load across the SOIC-8 leadframe. |
| 7 | Vin | power_in | Negative input supply (same net as pins 2, 3, 6). Ties into the internal input node of the regulator. |
| 8 | NC | unconnected | No internal connection. Not required for operation; may be left floating. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
MC79L05ACDR2GMC79L05ACDR2GDGMC79L05ACDR2GZGMC79L05ACDR2GRLRAGMC79L05ACDR2GRLRPG
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage (TJ = +25 C) | VO | -4.8 | -5 | -5.2 | Vdc | TJ = +25 C | 2 |
| Input Regulation (TJ = +25 C) | Regline | 150 | mV | TJ = +25 C; -7.0 Vdc VI -20 Vdc | 2 | ||
| Input Regulation (TJ = +25 C) | Regline | 100 | mV | TJ = +25 C; -8.0 Vdc VI -20 Vdc | 2 | ||
| Load Regulation | Regload | 60 | mV | TJ = +25 C, 1.0 mA IO 100 mA | 2 | ||
| Load Regulation | Regload | 30 | mV | 1.0 mA IO 40 mA | 2 | ||
| Output Voltage | VO | -4.75 | -5.25 | Vdc | -7.0 Vdc VI -20 Vdc, 1.0 mA IO 40 mA | 2 | |
| Input Bias Current (TJ = +25 C) | IIB | 6 | mA | TJ = +25 C | 2 | ||
| Input Bias Current (TJ = +125 C) | IIB | 5.5 | mA | TJ = +125 C | 2 | ||
| Input Bias Current Change | IIB | 1.5 | mA | -8.0 Vdc VI -20 Vdc | 2 | ||
| Input Bias Current Change | IIB | 0.1 | mA | 1.0 mA IO 40 mA | 2 | ||
| Ripple Rejection | RR | 41 | 49 | dB | -8.0 VI -18 Vdc, f = 120 Hz, TJ = +25 C | 2 | |
| Input Voltage (-5 V) | VI | -30 | Vdc | 2 | |||
| Storage Temperature Range | Tstg | -65 | 150 | C | 2 | ||
| Junction Temperature | TJ | 150 | C | 2 | |||
| Operating Junction Temperature (AC grade) | TJ | 0 | 125 | C | MC79LXXAC (0 C < TJ < +125 C) | 2 | |
| Thermal Resistance, Junction-to-Ambient (SOIC-8) | RJA | 180 | C/W | Case 751 (SOIC-8), TA = 25 C; minimum recommended pad size | 2 | ||
| Thermal Resistance, Junction-to-Case (SOIC-8) | RJC | 45 | C/W | Case 751 (SOIC-8) | 2 |
CAD (KiCad official)
- Symbol:
MC79L05ACDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mc79l05acdr2g-etched.step/mc79l05acdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc79l05acdr2g.step/mc79l05acdr2g.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
mc79l05acdr2g.step |
122 KB | You want the bare part, or you mark your own boards. |
mc79l05acdr2g-etched.step |
2.6 MB | You want the part with MC79L05ACDR2G already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 626 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (15 pp, sha256
3b8ec4831b4ba3d5, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC79L05ACDR2G
**onsemi** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
MC79L05ACDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vout | power_out | Regulated negative output voltage, nominally -5.0 V (-4.75 V to -5.25 V over line/load). Output current up to 100 mA (40 mA in SOIC-8 depending on thermal). A 0.1 uF output bypass capacitor is recommended for stability and transient response. |
| 2 | Vin | power_in | Unregulated negative input supply. Nominal operating range -7.0 V to -20 V for the -5 V version (absolute max -30 V). Pins 2, 3, 6, and 7 are all tied together internally as the input node; a 0.33 uF bypass capacitor to ground is recommended close to the pins. |
| 3 | Vin | power_in | Negative input supply (same net as pins 2, 6, 7). Multiple pins share the input node to reduce lead inductance and improve current handling on the SOIC-8 package. |
| 4 | NC | unconnected | No internal connection. Leave floating or tie to a convenient net for PCB routing; not required for operation. |
| 5 | GND | power_in | Common ground reference. Must be shared between input and output. Keep ground return short to avoid loop drops since the regulator has no external sense lead. |
| 6 | Vin | power_in | Negative input supply (same net as pins 2, 3, 7). Multiple Vin pins spread current and thermal load across the SOIC-8 leadframe. |
| 7 | Vin | power_in | Negative input supply (same net as pins 2, 3, 6). Ties into the internal input node of the regulator. |
| 8 | NC | unconnected | No internal connection. Not required for operation; may be left floating. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
## Ordering variants
Same part, different packaging or reel option.
- `MC79L05ACDR2G`
- `MC79L05ACDR2GDG`
- `MC79L05ACDR2GZG`
- `MC79L05ACDR2GRLRAG`
- `MC79L05ACDR2GRLRPG`
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage (TJ = +25 C) | VO | -4.8 | -5 | -5.2 | Vdc | TJ = +25 C | 2 |
| Input Regulation (TJ = +25 C) | Regline | | | 150 | mV | TJ = +25 C; -7.0 Vdc VI -20 Vdc | 2 |
| Input Regulation (TJ = +25 C) | Regline | | | 100 | mV | TJ = +25 C; -8.0 Vdc VI -20 Vdc | 2 |
| Load Regulation | Regload | | | 60 | mV | TJ = +25 C, 1.0 mA IO 100 mA | 2 |
| Load Regulation | Regload | | | 30 | mV | 1.0 mA IO 40 mA | 2 |
| Output Voltage | VO | -4.75 | | -5.25 | Vdc | -7.0 Vdc VI -20 Vdc, 1.0 mA IO 40 mA | 2 |
| Input Bias Current (TJ = +25 C) | IIB | | | 6 | mA | TJ = +25 C | 2 |
| Input Bias Current (TJ = +125 C) | IIB | | | 5.5 | mA | TJ = +125 C | 2 |
| Input Bias Current Change | IIB | | | 1.5 | mA | -8.0 Vdc VI -20 Vdc | 2 |
| Input Bias Current Change | IIB | | | 0.1 | mA | 1.0 mA IO 40 mA | 2 |
| Ripple Rejection | RR | 41 | 49 | | dB | -8.0 VI -18 Vdc, f = 120 Hz, TJ = +25 C | 2 |
| Input Voltage (-5 V) | VI | -30 | | | Vdc | | 2 |
| Storage Temperature Range | Tstg | -65 | | 150 | C | | 2 |
| Junction Temperature | TJ | | | 150 | C | | 2 |
| Operating Junction Temperature (AC grade) | TJ | 0 | | 125 | C | MC79LXXAC (0 C < TJ < +125 C) | 2 |
| Thermal Resistance, Junction-to-Ambient (SOIC-8) | RJA | | 180 | | C/W | Case 751 (SOIC-8), TA = 25 C; minimum recommended pad size | 2 |
| Thermal Resistance, Junction-to-Case (SOIC-8) | RJC | | 45 | | C/W | Case 751 (SOIC-8) | 2 |
## CAD (KiCad official)
- Symbol: `MC79L05ACDR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `mc79l05acdr2g-etched.step` / `mc79l05acdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc79l05acdr2g.step` / `mc79l05acdr2g.glb` are the bare package body.
## 3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
| [`mc79l05acdr2g.step`](mc79l05acdr2g.step) | 122 KB | You want the bare part, or you mark your own boards. |
| [`mc79l05acdr2g-etched.step`](mc79l05acdr2g-etched.step) | 2.6 MB | You want the part with `MC79L05ACDR2G` already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 626 faces against 147 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc79l05ac-d.pdf) (15 pp, sha256 `3b8ec4831b4ba3d5`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc79l05acdr2g-datasheet.pdf)