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MC74VHCT14ADR2G

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onsemi Logic ICs, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74VHCT14ADR2G

onsemi · Logic ICs · SOIC-14

MC74VHCT14ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Schmitt-trigger inverter input for channel 1; TTL-compatible (VIL 0.8 V max, VIH 2.0 V min) and protected for input voltages between 0 V and 5.5 V regardless of supply voltage.
2 Y1 output Inverted output of channel 1 (Y = A) with full 5.0 V CMOS output swing; maximum DC output source/sink current is 25 mA.
3 A2 input Schmitt-trigger inverter input for channel 2; TTL-compatible (VIL 0.8 V max, VIH 2.0 V min) and protected for input voltages between 0 V and 5.5 V regardless of supply voltage.
4 Y2 output Inverted output of channel 2 (Y = A) with full 5.0 V CMOS output swing; maximum DC output source/sink current is 25 mA.
5 A3 input Schmitt-trigger inverter input for channel 3; TTL-compatible (VIL 0.8 V max, VIH 2.0 V min) and protected for input voltages between 0 V and 5.5 V regardless of supply voltage.
6 Y3 output Inverted output of channel 3 (Y = A) with full 5.0 V CMOS output swing; maximum DC output source/sink current is 25 mA.
7 GND power_in Ground reference for the device; maximum ground current per ground pin is 50 mA.
8 Y4 output Inverted output of channel 4 (Y = A) with full 5.0 V CMOS output swing; maximum DC output source/sink current is 25 mA.
9 A4 input Schmitt-trigger inverter input for channel 4; TTL-compatible (VIL 0.8 V max, VIH 2.0 V min) and protected for input voltages between 0 V and 5.5 V regardless of supply voltage.
10 Y5 output Inverted output of channel 5 (Y = A) with full 5.0 V CMOS output swing; maximum DC output source/sink current is 25 mA.
11 A5 input Schmitt-trigger inverter input for channel 5; TTL-compatible (VIL 0.8 V max, VIH 2.0 V min) and protected for input voltages between 0 V and 5.5 V regardless of supply voltage.
12 Y6 output Inverted output of channel 6 (Y = A) with full 5.0 V CMOS output swing; maximum DC output source/sink current is 25 mA.
13 A6 input Schmitt-trigger inverter input for channel 6; TTL-compatible (VIL 0.8 V max, VIH 2.0 V min) and protected for input voltages between 0 V and 5.5 V regardless of supply voltage.
14 VCC power_in Positive supply; recommended operating range is 4.5 V to 5.5 V, with an absolute maximum DC supply voltage of 7.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 4.5 5.5 V 3
Input Voltage VI 0 5.5 V 3
Output Voltage VO 0 V 3
Output Voltage VO 0 5.5 V VCC = 0 V 3
Operating Free-Air Temperature TA -55 125 °C 3
DC Supply Voltage VCC -0.5 7 V 2
DC Input Voltage VIN -0.5 7 V 2
DC Output Voltage (output in HIGH or LOW state) VOUT -0.5 V Output in HIGH or LOW state (Note 1) 2
DC Output Voltage (VCC = 0 V) VOUT -0.5 7 V VCC = 0 V 2
DC Input Diode Current IIK -20 mA 2
DC Output Diode Current IOK 20 mA 2
DC Output Source/Sink Current IO 25 mA 2
DC Supply Current per Supply Pin ICC 50 mA 2
DC Ground Current per Ground Pin IGND 50 mA 2
Storage Temperature Range TSTG -65 150 °C 2
Lead Temperature TL 260 °C 1 mm from case for 10 seconds 2
Junction Temperature under Bias TJ 150 °C 2
Thermal Resistance, junction-to-ambient (SOIC) JA 125 °C/W SOIC package 2
ESD Withstand Voltage, Human Body Model VESD 2000 V Human Body Model (Note 2); printed >2000 V 2
Latchup Performance ILatchup 300 mA Above VCC and below GND at 85°C (Note 5) 2
Positive Threshold Voltage VT+ 1.9 2.1 V VCC = 4.5 V to 5.5 V; TA = 25°C 3
Negative Threshold Voltage VT- 0.5 0.6 V VCC = 4.5 V to 5.5 V; TA = 25°C 3
Hysteresis Voltage VH 0.4 1.4 V VCC = 4.5 V; TA = 25°C 3
Hysteresis Voltage VH 0.4 1.5 V VCC = 5.5 V; TA = 25°C 3
Minimum High-Level Output Voltage VOH 4.4 V VCC = 4.5 V; IOH = −50 µA; VIN = VIH or VIL; TA = 25°C 3
Minimum High-Level Output Voltage VOH 3.94 V VCC = 5.5 V; IOH = −8.0 mA; VIN = VIH or VIL; TA = 25°C 3
Minimum High-Level Output Voltage VOH 3.8 V VCC = 5.5 V; IOH = −8.0 mA; VIN = VIH or VIL; TA ≤ 85°C 3
Minimum High-Level Output Voltage VOH 3.66 V VCC = 5.5 V; IOH = −8.0 mA; VIN = VIH or VIL; TA ≤ 125°C 3
Maximum Low-Level Output Voltage VOL 0.1 V VCC = 4.5 V; IOL = 50 µA; VIN = VIH or VIL; TA = 25°C 3
Maximum Low-Level Output Voltage VOL 0.36 V VCC = 5.5 V; IOL = 8.0 mA; VIN = VIH or VIL; TA = 25°C 3
Maximum Low-Level Output Voltage VOL 0.44 V VCC = 5.5 V; IOL = 8.0 mA; VIN = VIH or VIL; TA ≤ 85°C 3
Maximum Low-Level Output Voltage VOL 0.52 V VCC = 5.5 V; IOL = 8.0 mA; VIN = VIH or VIL; TA ≤ 125°C 3
Maximum Input Leakage Current IIN -0.1 0.1 µA VIN = 5.5 V or GND; VCC = 0 to 5.5 V; TA = 25°C 3
Maximum Input Leakage Current IIN -1 1 µA VIN = 5.5 V or GND; VCC = 0 to 5.5 V; TA ≤ 85°C 3
Maximum Quiescent Supply Current ICC 2 µA VIN = VCC or GND; VCC = 5.5 V; TA = 25°C 3
Maximum Quiescent Supply Current ICC 20 µA VIN = VCC or GND; VCC = 5.5 V; TA ≤ 85°C 3
Maximum Quiescent Supply Current ICC 40 µA VIN = VCC or GND; VCC = 5.5 V; TA ≤ 125°C 3
Quiescent Supply Current ICCT 1.35 1.5 mA Input VIN = 3.4 V; VCC = 5.5 V; TA = 25°C 3
Quiescent Supply Current ICCT 1.65 mA Input VIN = 3.4 V; VCC = 5.5 V; TA ≤ 125°C 3
Output Leakage Current IOFF 0 0.5 µA VOUT = 5.5 V; VCC = 0 V; TA = 25°C 3
Output Leakage Current IOFF 5 µA VOUT = 5.5 V; VCC = 0 V; TA ≤ 85°C 3
Output Leakage Current IOFF 10 µA VOUT = 5.5 V; VCC = 0 V; TA ≤ 125°C 3
Maximum Propagation Delay, A to Y (CL = 15 pF) tPLH/tPHL 5.5 7 ns VCC = 5.0 ± 0.5 V; CL = 15 pF; TA = 25°C 3
Quiet Output Maximum Dynamic VOL VOLP 0.8 1 V Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V; TA = 25°C 3
Quiet Output Minimum Dynamic VOL VOLV -0.8 -1 V Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V; TA = 25°C 3
Minimum High-Level Dynamic Input Voltage VIHD 2 V Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V; TA = 25°C 3
Maximum Low-Level Dynamic Input Voltage VILD 0.8 V Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V; TA = 25°C 3

CAD (KiCad official)

  • Symbol: MC74VHCT14ADR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74vhct14adr2g-etched.step / mc74vhct14adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74vhct14adr2g.step / mc74vhct14adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 92c4922e88a9d589, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF