# MC74VHCT08ADTR2G

**onsemi** · Gates · TSSOP-14

MC74VHCT08ADTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Data input A of gate 1 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 2 | B1 | input | Data input B of gate 1 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 3 | Y1 | output | Output of gate 1 (Y = AB) with full 5.0 V CMOS level swing; DC output current limited to ±25 mA per pin, and unused outputs must be left open. |
| 4 | A2 | input | Data input A of gate 2 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 5 | B2 | input | Data input B of gate 2 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 6 | Y2 | output | Output of gate 2 (Y = AB) with full 5.0 V CMOS level swing; DC output current limited to ±25 mA per pin, and unused outputs must be left open. |
| 7 | GND | power_in | Ground pin; DC supply current through the VCC and GND pins is rated ±50 mA maximum. |
| 8 | Y3 | output | Output of gate 3 (Y = AB) with full 5.0 V CMOS level swing; DC output current limited to ±25 mA per pin, and unused outputs must be left open. |
| 9 | A3 | input | Data input A of gate 3 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 10 | B3 | input | Data input B of gate 3 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 11 | Y4 | output | Output of gate 4 (Y = AB) with full 5.0 V CMOS level swing; DC output current limited to ±25 mA per pin, and unused outputs must be left open. |
| 12 | A4 | input | Data input A of gate 4 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 13 | B4 | input | Data input B of gate 4 (Y = AB); TTL-compatible, with DC input voltage rated 0 V to 5.5 V, and unused inputs must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply; the device is specified for a DC supply of 2.0 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 |  | 7 | V |  | 2 |
| DC Input Voltage | Vin | -0.5 |  | 7 | V |  | 2 |
| DC Output Voltage | Vout | -0.5 |  |  | V | upper limit printed as VCC +0.5 V | 2 |
| Input Diode Current | IIK | -20 |  |  | mA | single value printed as −20 mA | 2 |
| Output Diode Current | IOK | -20 |  | 20 | mA |  | 2 |
| DC Output Current, per Pin | Iout | -25 |  | 25 | mA |  | 2 |
| DC Supply Current, VCC and GND Pins | ICC | -50 |  | 50 | mA |  | 2 |
| Power Dissipation in Still Air, TSSOP Package | PD |  |  | 450 | mW | TSSOP package, still air | 2 |
| Storage Temperature | Tstg | -65 |  | 150 | °C |  | 2 |
| DC Supply Voltage | VCC | 2 |  | 5.5 | V |  | 2 |
| DC Input Voltage | Vin | 0 |  | 5.5 | V |  | 2 |
| DC Output Voltage | Vout | 0 |  |  | V | upper limit printed as VCC | 2 |
| Operating Temperature | TA | -40 |  | 125 | °C |  | 2 |
| Input Rise and Fall Time | tr, tf | 0 |  | 20 | ns/V | VCC = 5.0 V ±0.5 V | 2 |
| Minimum High-Level Input Voltage | VIH | 1.2 |  |  | V | VCC = 3.0 V, TA = 25°C | 3 |
| Minimum High-Level Input Voltage | VIH | 2 |  |  | V | VCC = 4.5 V, TA = 25°C | 3 |
| Maximum Low-Level Input Voltage | VIL |  |  | 0.53 | V | VCC = 3.0 V, TA = 25°C | 3 |
| Maximum Low-Level Input Voltage | VIL |  |  | 0.8 | V | VCC = 4.5 V, TA = 25°C | 3 |
| Minimum High-Level Output Voltage | VOH | 2.9 |  |  | V | VIN = VIH or VIL, IOH = −50 µA, VCC = 3.0 V, TA = 25°C | 3 |
| Minimum High-Level Output Voltage | VOH | 4.4 |  |  | V | VIN = VIH or VIL, IOH = −50 µA, VCC = 4.5 V, TA = 25°C | 3 |
| Minimum High-Level Output Voltage | VOH | 2.58 |  |  | V | VIN = VIH or VIL, IOH = −4 mA, VCC = 3.0 V, TA = 25°C | 3 |
| Minimum High-Level Output Voltage | VOH | 2.34 |  |  | V | VIN = VIH or VIL, IOH = −4 mA, VCC = 3.0 V, TA ≤ 125°C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.94 |  |  | V | VIN = VIH or VIL, IOH = −8 mA, VCC = 4.5 V, TA = 25°C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.66 |  |  | V | VIN = VIH or VIL, IOH = −8 mA, VCC = 4.5 V, TA ≤ 125°C | 3 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.1 | V | VIN = VIH or VIL, IOL = 50 µA, VCC = 3.0 V, TA = 25°C | 3 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.36 | V | VIN = VIH or VIL, IOL = 4 mA, VCC = 3.0 V, TA = 25°C | 3 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.52 | V | VIN = VIH or VIL, IOL = 4 mA, VCC = 3.0 V, TA ≤ 125°C | 3 |
| Maximum Input Leakage Current | IIN | -0.1 |  | 0.1 | µA | VIN = 5.5 V or GND, VCC = 0 to 5.5 V, TA = 25°C | 3 |
| Maximum Input Leakage Current | IIN | -1 |  | 1 | µA | VIN = 5.5 V or GND, VCC = 0 to 5.5 V, TA ≤ 125°C | 3 |
| Maximum Quiescent Supply Current | ICC |  |  | 2 | µA | VIN = VCC or GND, VCC = 5.5 V, TA = 25°C | 3 |
| Maximum Quiescent Supply Current | ICC |  |  | 40 | µA | VIN = VCC or GND, VCC = 5.5 V, TA ≤ 125°C | 3 |
| Quiescent Supply Current | ICCT |  |  | 1.35 | mA | Input VIN = 3.4 V, VCC = 5.5 V, TA = 25°C | 3 |
| Quiescent Supply Current | ICCT |  |  | 1.65 | mA | Input VIN = 3.4 V, VCC = 5.5 V, TA ≤ 125°C | 3 |
| Output Leakage Current | IOPD |  |  | 0.5 | µA | VOUT = 5.5 V, VCC = 0.0 V, TA = 25°C | 3 |
| Output Leakage Current | IOPD |  |  | 10 | µA | VOUT = 5.5 V, VCC = 0.0 V, TA ≤ 125°C | 3 |
| Quiet Output Maximum Dynamic VOL | VOLP |  | 0.3 | 0.8 | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 3 |
| Quiet Output Minimum Dynamic VOL | VOLV | -0.8 | -0.3 |  | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 3 |
| Minimum High Level Dynamic Input Voltage | VIHD | 3.5 |  |  | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 3 |
| Maximum Low Level Dynamic Input Voltage | VILD |  |  | 1.5 | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 3 |
| Maximum Input Capacitance | Cin |  | 4 | 10 | pF |  | 3 |

## CAD (KiCad official)

- Symbol: `MC74VHCT08ADTR2G`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `mc74vhct08adtr2g-etched.step` / `mc74vhct08adtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74vhct08adtr2g.step` / `mc74vhct08adtr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74vhct08adtr2-d.pdf) (8 pp, sha256 `21e61f6e91c1f52c`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mc74vhct08adtr2g-datasheet.pdf)