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MC74VHCT04ADR2G

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onsemi Inverters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74VHCT04ADR2G

onsemi · Inverters · SOIC-14

MC74VHCT04ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input of inverter 1; inputs tolerate voltages up to 7 V and recommended Vin is 0 V to 5.5 V, with TTL-compatible thresholds (VIL max 0.8 V, VIH min 2.0 V at VCC 4.5 V to 5.5 V).
2 Y1 output Output of inverter 1 (Y = A), with full 5 V CMOS level output swing and DC output current limited to ±25 mA per pin.
3 A2 input Input of inverter 2; inputs tolerate voltages up to 7 V and recommended Vin is 0 V to 5.5 V, with TTL-compatible thresholds (VIL max 0.8 V, VIH min 2.0 V at VCC 4.5 V to 5.5 V).
4 Y2 output Output of inverter 2 (Y = A), with full 5 V CMOS level output swing and DC output current limited to ±25 mA per pin.
5 A3 input Input of inverter 3; inputs tolerate voltages up to 7 V and recommended Vin is 0 V to 5.5 V, with TTL-compatible thresholds (VIL max 0.8 V, VIH min 2.0 V at VCC 4.5 V to 5.5 V).
6 Y3 output Output of inverter 3 (Y = A), with full 5 V CMOS level output swing and DC output current limited to ±25 mA per pin.
7 GND power_in Ground reference for the device.
8 Y4 output Output of inverter 4 (Y = A), with full 5 V CMOS level output swing and DC output current limited to ±25 mA per pin.
9 A4 input Input of inverter 4; inputs tolerate voltages up to 7 V and recommended Vin is 0 V to 5.5 V, with TTL-compatible thresholds (VIL max 0.8 V, VIH min 2.0 V at VCC 4.5 V to 5.5 V).
10 Y5 output Output of inverter 5 (Y = A), with full 5 V CMOS level output swing and DC output current limited to ±25 mA per pin.
11 A5 input Input of inverter 5; inputs tolerate voltages up to 7 V and recommended Vin is 0 V to 5.5 V, with TTL-compatible thresholds (VIL max 0.8 V, VIH min 2.0 V at VCC 4.5 V to 5.5 V).
12 Y6 output Output of inverter 6 (Y = A), with full 5 V CMOS level output swing and DC output current limited to ±25 mA per pin.
13 A6 input Input of inverter 6; inputs tolerate voltages up to 7 V and recommended Vin is 0 V to 5.5 V, with TTL-compatible thresholds (VIL max 0.8 V, VIH min 2.0 V at VCC 4.5 V to 5.5 V).
14 VCC power_in Positive supply; recommended DC supply voltage range is 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC 4.5 5.5 V 3
DC Input Voltage Vin 0 5.5 V 3
DC Output Voltage Vout 0 5.5 V VCC = 0; high or low state 3
DC Output Voltage Vout 0 V High or low state; printed max is VCC 3
Operating Temperature TA -40 85 °C 3
Input Rise and Fall Time tr, tf 0 20 ns/V VCC = 5.0 V ±0.5 V 3
DC Supply Voltage VCC -0.5 7 V 3
DC Input Voltage Vin -0.5 7 V 3
DC Output Voltage Vout -0.5 7 V VCC = 0; high or low state 3
DC Output Voltage Vout -0.5 V High or low state; printed max is VCC + 0.5 3
Input Diode Current IIK -20 mA 3
Output Diode Current IOK -20 20 mA VOUT < GND; VOUT > VCC 3
DC Output Current, per Pin Iout -25 25 mA 3
DC Supply Current, VCC and GND Pins ICC -50 50 mA 3
Power Dissipation in Still Air PD 500 mW SOIC packages; derate 7 mW/°C from 65 to 125°C 3
Storage Temperature Tstg -65 150 °C 3
Minimum High-Level Input Voltage VIH 2 V VCC = 4.5 to 5.5 V; TA = 25°C 3
Maximum Low-Level Input Voltage VIL 0.8 V VCC = 4.5 to 5.5 V; TA = 25°C 3
Minimum High-Level Output Voltage VOH 4.4 4.5 V VCC = 4.5 V; Vin = VIH or VIL; IOH = −50 μA; TA = 25°C 3
Minimum High-Level Output Voltage VOH 4.4 V VCC = 4.5 V; Vin = VIH or VIL; IOH = −50 μA; TA = −40 to 85°C 3
Minimum High-Level Output Voltage VOH 3.94 V VCC = 4.5 V; Vin = VIH or VIL; IOH = −8 mA; TA = 25°C 3
Minimum High-Level Output Voltage VOH 3.8 V VCC = 4.5 V; Vin = VIH or VIL; IOH = −8 mA; TA = −40 to 85°C 3
Maximum Low-Level Output Voltage VOL 0 0.1 V VCC = 4.5 V; Vin = VIH or VIL; IOL = 50 μA; TA = 25°C 3
Maximum Low-Level Output Voltage VOL 0.1 V VCC = 4.5 V; Vin = VIH or VIL; IOL = 50 μA; TA = −40 to 85°C 3
Maximum Low-Level Output Voltage VOL 0.36 0.44 V VCC = 4.5 V; Vin = VIH or VIL; IOL = 8 mA; TA = 25°C 3
Maximum Low-Level Output Voltage VOL 0.44 V VCC = 4.5 V; Vin = VIH or VIL; IOL = 8 mA; TA = −40 to 85°C 3
Maximum Input Leakage Current Iin -0.1 0.1 μA Vin = 5.5 V or GND; VCC = 0 to 5.5 V; TA = 25°C 3
Maximum Input Leakage Current Iin -1 1 μA Vin = 5.5 V or GND; VCC = 0 to 5.5 V; TA = −40 to 85°C 3
Maximum Quiescent Supply Current ICC 2 μA VCC = 5.5 V; Vin = VCC or GND; TA = 25°C 3
Maximum Quiescent Supply Current ICC 20 μA VCC = 5.5 V; Vin = VCC or GND; TA = −40 to 85°C 3
Quiescent Supply Current ICCT 1.35 mA VCC = 5.5 V; per input VIN = 3.4 V; other input VCC or GND; TA = 25°C 3
Quiescent Supply Current ICCT 1.5 mA VCC = 5.5 V; per input VIN = 3.4 V; other input VCC or GND; TA = −40 to 85°C 3
Output Leakage Current IOPD 0.5 μA VCC = 0 V; VOUT = 5.5 V; TA = 25°C 3
Output Leakage Current IOPD 5 μA VCC = 0 V; VOUT = 5.5 V; TA = −40 to 85°C 3
Maximum Propagation Delay, A to Y tPLH, tPHL 1 4.7 5.5 ns VCC = 5.0 ±0.5 V; CL = 15 pF; TA = 25°C; input tr = tf = 3.0 ns 4
Maximum Propagation Delay, A to Y tPLH, tPHL 1 6.7 7.7 ns VCC = 5.0 ±0.5 V; CL = 50 pF; TA = 25°C; input tr = tf = 3.0 ns 4
Maximum Propagation Delay, A to Y tPLH, tPHL 1 7.5 ns VCC = 5.0 ±0.5 V; CL = 15 pF; TA = −40 to 85°C; input tr = tf = 3.0 ns 4
Maximum Propagation Delay, A to Y tPLH, tPHL 1 8.5 ns VCC = 5.0 ±0.5 V; CL = 50 pF; TA = −40 to 85°C; input tr = tf = 3.0 ns 4
Maximum Input Capacitance Cin 4 10 pF TA = 25°C 4
Maximum Input Capacitance Cin 10 pF TA = −40 to 85°C 4
Power Dissipation Capacitance CPD 11 pF Typical @ 25°C, VCC = 5.0 V 4
Quiet Output Maximum Dynamic VOL VOLP 0.8 1 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 4
Quiet Output Minimum Dynamic VOL VOLV -0.8 -1 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 4
Minimum High Level Dynamic Input Voltage VIHD 2 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 4
Maximum Low Level Dynamic Input Voltage VILD 0.8 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 4

CAD (KiCad official)

  • Symbol: MC74VHCT04ADR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74vhct04adr2g-etched.step / mc74vhct04adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74vhct04adr2g.step / mc74vhct04adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 1af38c66de8e3c15, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF