component
MC74VHC50DR2G
Public Made by Adomby adom
onsemi Buffers, Drivers, Receivers, Transceivers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74VHC50DR2G
onsemi · Buffers, Drivers, Receivers, Transceivers · SOIC-14
MC74VHC50DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Buffer 1 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 2 | Y1 | output | Buffer 1 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 3 | A2 | input | Buffer 2 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 4 | Y2 | output | Buffer 2 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 5 | A3 | input | Buffer 3 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 6 | Y3 | output | Buffer 3 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | Y4 | output | Buffer 4 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 9 | A4 | input | Buffer 4 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 10 | Y5 | output | Buffer 5 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 11 | A5 | input | Buffer 5 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 12 | Y6 | output | Buffer 6 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 13 | A6 | input | Buffer 6 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 14 | VCC | power_in | Positive supply; the DC supply voltage range is 2.0 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (recommended operating, MC74VHC) | VCC | 2 | 5.5 | V | MC74VHC | 4 | |
| DC Input Voltage (recommended, MC74VHC) | VI | 0 | 5.5 | V | Note 5 | 4 | |
| DC Output Voltage (recommended, MC74VHC) | VO | 0 | V | Printed upper limit is VCC (Note 5) | 4 | ||
| Operating Temperature | TA | -55 | 125 | °C | 4 | ||
| Input Rise or Fall Rate | tr, tf | 0 | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 | |
| Input Rise or Fall Rate | tr, tf | 0 | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 | |
| DC Supply Voltage (absolute maximum) | VCC | -0.5 | 6.5 | V | 3 | ||
| DC Input Voltage (absolute maximum) | VI | -0.5 | 6.5 | V | 3 | ||
| DC Output Voltage (absolute maximum, MC74VHC) | VO | -0.5 | V | Printed upper limit is VCC + 0.5 V | 3 | ||
| DC Input Current, per Pin | IIN | -20 | 20 | mA | 3 | ||
| DC Output Current, Per Pin | IOUT | -25 | 25 | mA | 3 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 3 | ||
| Input Clamp Current | IIK | -20 | mA | 3 | |||
| Output Clamp Current (MC74VHC) | IOK | -20 | 20 | mA | 3 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Junction Temperature Under Bias | TJ | 150 | °C | 3 | |||
| Thermal Resistance, Junction-to-Ambient | θJA | 116 | °C/W | SOIC-14 NB; Note 2 (minimum pad spacing, FR4, 76 mm x 114 mm 2-oz copper, JESD51-7, no air flow) | 3 | ||
| ESD Withstand Voltage, Human Body Model | VESD | 2000 | V | Human Body Model; printed as > 2000 (Note 3) | 3 | ||
| Latchup Performance | ILATCHUP | -100 | 100 | mA | Note 4, EIA/JESD78 Class II | 3 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; TA = 25 °C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 2 | V | VCC = 3.0 V; TA = 25 °C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; TA = 25 °C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.85 | V | VCC = 5.5 V; TA = 25 °C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; TA = 25 °C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V; TA = 25 °C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; TA = 25 °C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.65 | V | VCC = 5.5 V; TA = 25 °C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 2.0 V; TA = 25 °C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 2.9 | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 3.0 V; TA = 25 °C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 4.5 V; TA = 25 °C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 2.58 | V | VIN = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA = 25 °C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 2.34 | V | VIN = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA ≤ 125 °C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.94 | V | VIN = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA = 25 °C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.66 | V | VIN = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA ≤ 125 °C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VIN = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = 25 °C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.36 | V | VIN = VIH or VIL; IOL = 4 mA; VCC = 3.0 V; TA = 25 °C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.52 | V | VIN = VIH or VIL; IOL = 4 mA; VCC = 3.0 V; TA ≤ 125 °C | 4 | ||
| Maximum Input Leakage Current | IIN | -0.1 | 0.1 | µA | VIN = 5.5 V or GND 0 to 5.5; TA = 25 °C | 4 | |
| Maximum Input Leakage Current | IIN | -1 | 1 | µA | VIN = 5.5 V or GND 0 to 5.5; TA ≤ 85 °C | 4 | |
| Maximum Quiescent Supply Current | ICC | 2 | µA | VIN = VCC or GND; VCC = 5.5 V; TA = 25 °C | 4 | ||
| Maximum Quiescent Supply Current | ICC | 20 | µA | VIN = VCC or GND; VCC = 5.5 V; TA ≤ 85 °C | 4 | ||
| Maximum Quiescent Supply Current | ICC | 40 | µA | VIN = VCC or GND; VCC = 5.5 V; TA ≤ 125 °C | 4 | ||
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 5 | 7.1 | ns | VCC = 3.0 ± 0.3 V; CL = 15 pF; TA = 25 °C (typ and max) | 5 | |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 10 | ns | VCC = 3.0 ± 0.3 V; CL = 15 pF; TA ≤ 125 °C | 5 | ||
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 7.5 | 10.6 | ns | VCC = 3.0 ± 0.3 V; CL = 50 pF; TA = 25 °C (typ and max) | 5 | |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 14.5 | ns | VCC = 3.0 ± 0.3 V; CL = 50 pF; TA ≤ 125 °C | 5 | ||
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 3.8 | 5.5 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; TA = 25 °C (typ and max) | 5 | |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 8 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; TA ≤ 125 °C | 5 | ||
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 5.3 | 7.5 | ns | VCC = 5.0 ± 0.5 V; CL = 50 pF; TA = 25 °C (typ and max) | 5 | |
| Maximum Input Capacitance | CIN | 4 | 10 | pF | TA = 25 °C | 5 | |
| Quiet Output Maximum Dynamic VOL | VOLP | 0.8 | 1 | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 | |
| Quiet Output Minimum Dynamic VOL | VOLV | -1 | -0.8 | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 | |
| Minimum High Level Dynamic Input Voltage | VIHD | 3.5 | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 | ||
| Maximum Low Level Dynamic Input Voltage | VILD | 1.5 | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 |
CAD (KiCad official)
- Symbol:
MC74VHC50DR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74vhc50dr2g-etched.step/mc74vhc50dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74vhc50dr2g.step/mc74vhc50dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
22d698befb8abab0, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74VHC50DR2G
**onsemi** · Buffers, Drivers, Receivers, Transceivers · SOIC-14
MC74VHC50DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Buffer 1 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 2 | Y1 | output | Buffer 1 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 3 | A2 | input | Buffer 2 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 4 | Y2 | output | Buffer 2 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 5 | A3 | input | Buffer 3 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 6 | Y3 | output | Buffer 3 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | Y4 | output | Buffer 4 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 9 | A4 | input | Buffer 4 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 10 | Y5 | output | Buffer 5 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 11 | A5 | input | Buffer 5 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 12 | Y6 | output | Buffer 6 output, where Y = A; the MC74VHC50 output swings to full 5.0 V CMOS levels. |
| 13 | A6 | input | Buffer 6 input; inputs are power-down protected and the recommended input voltage range is 0 V to 5.5 V. |
| 14 | VCC | power_in | Positive supply; the DC supply voltage range is 2.0 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (recommended operating, MC74VHC) | VCC | 2 | | 5.5 | V | MC74VHC | 4 |
| DC Input Voltage (recommended, MC74VHC) | VI | 0 | | 5.5 | V | Note 5 | 4 |
| DC Output Voltage (recommended, MC74VHC) | VO | 0 | | | V | Printed upper limit is VCC (Note 5) | 4 |
| Operating Temperature | TA | -55 | | 125 | °C | | 4 |
| Input Rise or Fall Rate | tr, tf | 0 | | 100 | ns/V | VCC = 3.0 V to 3.6 V | 4 |
| Input Rise or Fall Rate | tr, tf | 0 | | 20 | ns/V | VCC = 4.5 V to 5.5 V | 4 |
| DC Supply Voltage (absolute maximum) | VCC | -0.5 | | 6.5 | V | | 3 |
| DC Input Voltage (absolute maximum) | VI | -0.5 | | 6.5 | V | | 3 |
| DC Output Voltage (absolute maximum, MC74VHC) | VO | -0.5 | | | V | Printed upper limit is VCC + 0.5 V | 3 |
| DC Input Current, per Pin | IIN | -20 | | 20 | mA | | 3 |
| DC Output Current, Per Pin | IOUT | -25 | | 25 | mA | | 3 |
| DC Supply Current, VCC and GND Pins | ICC | -50 | | 50 | mA | | 3 |
| Input Clamp Current | IIK | -20 | | | mA | | 3 |
| Output Clamp Current (MC74VHC) | IOK | -20 | | 20 | mA | | 3 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 3 |
| Junction Temperature Under Bias | TJ | | | 150 | °C | | 3 |
| Thermal Resistance, Junction-to-Ambient | θJA | | 116 | | °C/W | SOIC-14 NB; Note 2 (minimum pad spacing, FR4, 76 mm x 114 mm 2-oz copper, JESD51-7, no air flow) | 3 |
| ESD Withstand Voltage, Human Body Model | VESD | 2000 | | | V | Human Body Model; printed as > 2000 (Note 3) | 3 |
| Latchup Performance | ILATCHUP | -100 | | 100 | mA | Note 4, EIA/JESD78 Class II | 3 |
| Minimum High-Level Input Voltage | VIH | 1.5 | | | V | VCC = 2.0 V; TA = 25 °C | 4 |
| Minimum High-Level Input Voltage | VIH | 2 | | | V | VCC = 3.0 V; TA = 25 °C | 4 |
| Minimum High-Level Input Voltage | VIH | 3.15 | | | V | VCC = 4.5 V; TA = 25 °C | 4 |
| Minimum High-Level Input Voltage | VIH | 3.85 | | | V | VCC = 5.5 V; TA = 25 °C | 4 |
| Maximum Low-Level Input Voltage | VIL | | | 0.5 | V | VCC = 2.0 V; TA = 25 °C | 4 |
| Maximum Low-Level Input Voltage | VIL | | | 0.9 | V | VCC = 3.0 V; TA = 25 °C | 4 |
| Maximum Low-Level Input Voltage | VIL | | | 1.35 | V | VCC = 4.5 V; TA = 25 °C | 4 |
| Maximum Low-Level Input Voltage | VIL | | | 1.65 | V | VCC = 5.5 V; TA = 25 °C | 4 |
| Minimum High-Level Output Voltage | VOH | 1.9 | | | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 2.0 V; TA = 25 °C | 4 |
| Minimum High-Level Output Voltage | VOH | 2.9 | | | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 3.0 V; TA = 25 °C | 4 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 4.5 V; TA = 25 °C | 4 |
| Minimum High-Level Output Voltage | VOH | 2.58 | | | V | VIN = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA = 25 °C | 4 |
| Minimum High-Level Output Voltage | VOH | 2.34 | | | V | VIN = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA ≤ 125 °C | 4 |
| Minimum High-Level Output Voltage | VOH | 3.94 | | | V | VIN = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA = 25 °C | 4 |
| Minimum High-Level Output Voltage | VOH | 3.66 | | | V | VIN = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA ≤ 125 °C | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VIN = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = 25 °C | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.36 | V | VIN = VIH or VIL; IOL = 4 mA; VCC = 3.0 V; TA = 25 °C | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.52 | V | VIN = VIH or VIL; IOL = 4 mA; VCC = 3.0 V; TA ≤ 125 °C | 4 |
| Maximum Input Leakage Current | IIN | -0.1 | | 0.1 | µA | VIN = 5.5 V or GND 0 to 5.5; TA = 25 °C | 4 |
| Maximum Input Leakage Current | IIN | -1 | | 1 | µA | VIN = 5.5 V or GND 0 to 5.5; TA ≤ 85 °C | 4 |
| Maximum Quiescent Supply Current | ICC | | | 2 | µA | VIN = VCC or GND; VCC = 5.5 V; TA = 25 °C | 4 |
| Maximum Quiescent Supply Current | ICC | | | 20 | µA | VIN = VCC or GND; VCC = 5.5 V; TA ≤ 85 °C | 4 |
| Maximum Quiescent Supply Current | ICC | | | 40 | µA | VIN = VCC or GND; VCC = 5.5 V; TA ≤ 125 °C | 4 |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | | 5 | 7.1 | ns | VCC = 3.0 ± 0.3 V; CL = 15 pF; TA = 25 °C (typ and max) | 5 |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | | | 10 | ns | VCC = 3.0 ± 0.3 V; CL = 15 pF; TA ≤ 125 °C | 5 |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | | 7.5 | 10.6 | ns | VCC = 3.0 ± 0.3 V; CL = 50 pF; TA = 25 °C (typ and max) | 5 |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | | | 14.5 | ns | VCC = 3.0 ± 0.3 V; CL = 50 pF; TA ≤ 125 °C | 5 |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | | 3.8 | 5.5 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; TA = 25 °C (typ and max) | 5 |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | | | 8 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; TA ≤ 125 °C | 5 |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | | 5.3 | 7.5 | ns | VCC = 5.0 ± 0.5 V; CL = 50 pF; TA = 25 °C (typ and max) | 5 |
| Maximum Input Capacitance | CIN | | 4 | 10 | pF | TA = 25 °C | 5 |
| Quiet Output Maximum Dynamic VOL | VOLP | | 0.8 | 1 | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 |
| Quiet Output Minimum Dynamic VOL | VOLV | -1 | -0.8 | | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 |
| Minimum High Level Dynamic Input Voltage | VIHD | 3.5 | | | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 |
| Maximum Low Level Dynamic Input Voltage | VILD | | | 1.5 | V | CL = 50 pF; VCC = 5.0 V; TA = 25 °C | 5 |
## CAD (KiCad official)
- Symbol: `MC74VHC50DR2G`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mc74vhc50dr2g-etched.step` / `mc74vhc50dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74vhc50dr2g.step` / `mc74vhc50dr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74vhc50-d.pdf) (13 pp, sha256 `22d698befb8abab0`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74vhc50dr2g-datasheet.pdf)