component
MC74VHC50DG
Public Made by Adomby adom
onsemi Buffers / Drivers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74VHC50DG
onsemi · Buffers / Drivers · SOIC-14
MC74VHC50DG from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Buffer 1 input; tolerates up to 7 V and must be tied to a high or low logic level, not left open. |
| 2 | Y1 | output | Buffer 1 output (Y = A), buffered output stage. |
| 3 | A2 | input | Buffer 2 input; tolerates up to 7 V and must be tied to a high or low logic level, not left open. |
| 4 | Y2 | output | Buffer 2 output (Y = A), buffered output stage. |
| 5 | A3 | input | Buffer 3 input; tolerates up to 7 V and must be tied to a high or low logic level, not left open. |
| 6 | Y3 | output | Buffer 3 output (Y = A), buffered output stage. |
| 7 | GND | power_in | Ground (0 V) reference. |
| 8 | Y4 | output | Buffer 4 output (Y = A), buffered output stage. |
| 9 | A4 | input | Buffer 4 input; tolerates up to 7 V and must be tied to a high or low logic level, not left open. |
| 10 | Y5 | output | Buffer 5 output (Y = A), buffered output stage. |
| 11 | A5 | input | Buffer 5 input; tolerates up to 7 V and must be tied to a high or low logic level, not left open. |
| 12 | Y6 | output | Buffer 6 output (Y = A), buffered output stage. |
| 13 | A6 | input | Buffer 6 input; tolerates up to 7 V and must be tied to a high or low logic level, not left open. |
| 14 | VCC | power_in | Positive supply, 2.0 V to 5.5 V recommended operating range (absolute maximum 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Voltage | VIN | -0.5 | 7 | V | 3 | ||
| DC Output Voltage | VOUT | -0.5 | 7.5 | V | -0.5 to VCC + 0.5 V; the upper limit is VCC + 0.5 | 3 | |
| DC Input Diode Current | IIK | -20 | mA | VI < GND | 3 | ||
| DC Output Diode Current | IOK | -20 | mA | VO < GND | 3 | ||
| DC Output Sink Current | IOUT | 25 | mA | 3 | |||
| DC Supply Current per Supply Pin | ICC | 50 | mA | 3 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from Case for 10 Seconds | 3 | ||
| Junction Temperature under Bias | TJ | 150 | °C | 3 | |||
| Thermal Resistance, SOIC | θJA | 125 | °C/W | SOIC, Note 1 | 3 | ||
| Latch-Up Performance | ILatch-Up | 300 | mA | Above VCC and Below GND at 85°C (Note 5) | 3 | ||
| Supply Voltage | VCC | 2 | 5.5 | V | 3 | ||
| Input Voltage | VI | 0 | 5.5 | V | Note 6 | 3 | |
| Output Voltage | VO | 0 | V | HIGH or LOW State; max is VCC | 3 | ||
| Operating Free-Air Temperature | TA | -55 | 125 | °C | 3 | ||
| Input Transition Rise or Fall Rate | Δt/ΔV | 0 | 100 | ns/V | VCC = 3.0 V ± 0.3 V | 3 | |
| Input Transition Rise or Fall Rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 3 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V, TA = 25°C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 2 | V | VCC = 3.0 V, TA = 25°C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V, TA = 25°C | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.85 | V | VCC = 5.5 V, TA = 25°C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V, TA = 25°C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V, TA = 25°C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V, TA = 25°C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.65 | V | VCC = 5.5 V, TA = 25°C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | 2 | V | VIN = VIH or VIL, IOH = -50 µA, VCC = 2.0 V, TA = 25°C | 4 | |
| Minimum High-Level Output Voltage | VOH | 2.9 | 3 | V | VIN = VIH or VIL, IOH = -50 µA, VCC = 3.0 V, TA = 25°C | 4 | |
| Minimum High-Level Output Voltage | VOH | 4.4 | 4.5 | V | VIN = VIH or VIL, IOH = -50 µA, VCC = 4.5 V, TA = 25°C | 4 | |
| Minimum High-Level Output Voltage | VOH | 2.58 | V | VIN = VIH or VIL, IOH = -4 mA, VCC = 3.0 V, TA = 25°C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.94 | V | VIN = VIH or VIL, IOH = -8 mA, VCC = 4.5 V, TA = 25°C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0 | 0.1 | V | VIN = VIH or VIL, IOL = 50 µA, VCC = 2.0 V, TA = 25°C | 4 | |
| Maximum Low-Level Output Voltage | VOL | 0.36 | V | VIN = VIH or VIL, IOL = 4 mA, VCC = 3.0 V, TA = 25°C | 4 | ||
| Maximum Input Leakage Current | IIN | -0.1 | 0.1 | µA | VIN = 5.5 V or GND, VCC = 0 to 5.5 V, TA = 25°C | 4 | |
| Maximum Input Leakage Current | IIN | -1 | 1 | µA | VIN = 5.5 V or GND, VCC = 0 to 5.5 V, TA ≤ 85°C | 4 | |
| Maximum Quiescent Supply Current | ICC | 2 | µA | VIN = VCC or GND, VCC = 5.5 V, TA = 25°C | 4 | ||
| Maximum Quiescent Supply Current | ICC | 20 | µA | VIN = VCC or GND, VCC = 5.5 V, TA ≤ 85°C | 4 | ||
| Maximum Quiescent Supply Current | ICC | 40 | µA | VIN = VCC or GND, VCC = 5.5 V, TA ≤ 125°C | 4 | ||
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 5 | 7.1 | ns | VCC = 3.0 ± 0.3 V, CL = 15 pF, TA = 25°C | 4 | |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 7.5 | 10.6 | ns | VCC = 3.0 ± 0.3 V, CL = 50 pF, TA = 25°C | 4 | |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 3.8 | 5.5 | ns | VCC = 5.0 ± 0.5 V, CL = 15 pF, TA = 25°C | 4 | |
| Maximum Propagation Delay, Input A to Y | tPLH, tPHL | 5.3 | 7.5 | ns | VCC = 5.0 ± 0.5 V, CL = 50 pF, TA = 25°C | 4 | |
| Maximum Input Capacitance | CIN | 4 | 10 | pF | TA = 25°C | 4 | |
| Power Dissipation Capacitance | CPD | 18 | pF | Typical @ 25°C, VCC = 5.0 V (Note 7) | 4 | ||
| Quiet Output Maximum Dynamic VOL | VOLP | 0.8 | 1 | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 4 | |
| Quiet Output Minimum Dynamic VOL | VOLV | -0.8 | -1 | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 4 | |
| Minimum High Level Dynamic Input Voltage | VIHD | 3.5 | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 4 | ||
| Maximum Low Level Dynamic Input Voltage | VILD | 1.5 | V | Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, TA = 25°C | 4 |
CAD (KiCad official)
- Symbol:
MC74VHC50DG - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74vhc50dg-etched.step/mc74vhc50dg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74vhc50dg.step/mc74vhc50dg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
09cadfb29d4701a4, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).