component
MC74VHC4053DR2G
Public Made by Adomby adom
onsemi Analog Switches, Multiplexers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74VHC4053DR2G
onsemi · Analog Switches, Multiplexers · SOIC-16
MC74VHC4053DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | passive | Analog input/output of the Y-switch channel Y1; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 2 | Y0 | passive | Analog input/output of the Y-switch channel Y0; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 3 | Z1 | passive | Analog input/output of the Z-switch channel Z1; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 4 | Z | passive | Common output/input of the Z switch; it connects to Z0 or Z1 under control of Channel-Select input C, and analog voltage must stay between VEE and VCC. |
| 5 | Z0 | passive | Analog input/output of the Z-switch channel Z0; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 6 | ENABLE | input | Active-high enable; when HIGH all analog switches are turned off, and the input is CMOS-compatible with a 0 V to VCC logic range (pull-up resistors needed for LSTTL outputs). |
| 7 | VEE | power_in | Negative DC supply for the analog section, which must satisfy VEE − GND = 0 to −6 V and VEE ≤ GND, with VCC − VEE = 2 to 12 V. |
| 8 | GND | power_in | Digital ground reference for the control inputs, with VCC − GND = 2 to 6 V recommended. |
| 9 | C | input | Channel-Select input C that controls the Z switch; it must be driven at VCC or GND logic levels (0 V to VCC). |
| 10 | B | input | Channel-Select input B that controls the Y switch; it must be driven at VCC or GND logic levels (0 V to VCC). |
| 11 | A | input | Channel-Select input A that controls the X switch; it must be driven at VCC or GND logic levels (0 V to VCC). |
| 12 | X0 | passive | Analog input/output of the X-switch channel X0; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 13 | X1 | passive | Analog input/output of the X-switch channel X1; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 14 | X | passive | Common output/input of the X switch; it connects to X0 or X1 under control of Channel-Select input A, and analog voltage must stay between VEE and VCC. |
| 15 | Y | passive | Common output/input of the Y switch; it connects to Y0 or Y1 under control of Channel-Select input B, and analog voltage must stay between VEE and VCC. |
| 16 | VCC | power_in | Positive DC supply, referenced to GND at 2.0 to 6.0 V and to VEE at 2.0 to 12.0 V (absolute maximum 7.0 V to GND and 14.0 V to VEE). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 4 | |
| Positive DC Supply Voltage (Referenced to VEE) | VCC | -0.5 | 14 | V | Referenced to VEE | 4 | |
| Negative DC Supply Voltage (Referenced to GND) | VEE | -7 | 5 | V | Referenced to GND | 4 | |
| DC Current, Into or Out of Any Pin | I | -25 | 25 | mA | 4 | ||
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | Still air, SOIC package; derate -7 mW/°C from 65 to 125°C | 4 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 4 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 4 | ||
| Positive DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 4 | |
| Positive DC Supply Voltage (Referenced to VEE) | VCC | 2 | 12 | V | Referenced to VEE | 4 | |
| Negative DC Supply Voltage, Output (Referenced to GND) | VEE | -6 | V | Maximum printed as GND (not a number) | 4 | ||
| Static or Dynamic Voltage Across Switch | VIO* | 1.2 | V | Footnote: above 1.2 V (switch on) excessive VCC current may be drawn | 4 | ||
| Operating Temperature Range, All Package Types | TA | -55 | 125 | °C | 4 | ||
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 4 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 800 | ns | VCC = 3.0 V | 4 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 4 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 4 | |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 1.5 | V | VCC = 2.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 2.1 | V | VCC = 3.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 3.15 | V | VCC = 4.5 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 4.2 | V | VCC = 6.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 0.5 | V | VCC = 2.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 0.9 | V | VCC = 3.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 1.35 | V | VCC = 4.5 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 1.8 | V | VCC = 6.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 | ||
| Maximum Input Leakage Current, Channel-Select or Enable Inputs | Iin | -0.1 | 0.1 | µA | Vin = VCC or GND; VEE = −6.0 V; VCC = 6.0 V; −55 to 25°C | 5 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 1 | µA | VCC = 6.0 V; VEE = GND; VIS = VCC or GND; VIO = 0 V; −55 to 25°C | 5 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | VCC = 6.0 V; VEE = −6.0 V; VIS = VCC or GND; VIO = 0 V; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron) | Ron | 200 | Ω | VCC = 3.0 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron) | Ron | 160 | Ω | VCC = 4.5 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron) | Ron | 120 | Ω | VCC = 4.5 V; VEE = −4.5 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron) | Ron | 100 | Ω | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron), endpoints | Ron | 150 | Ω | VCC = 3.0 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron), endpoints | Ron | 110 | Ω | VCC = 4.5 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron), endpoints | Ron | 90 | Ω | VCC = 4.5 V; VEE = −4.5 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum ON Resistance (Ron), endpoints | Ron | 80 | Ω | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum Difference in ON Resistance Between Any Two Channels in Same Package (ΔRon) | ΔRon | 40 | Ω | VCC = 3.0 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum Difference in ON Resistance Between Any Two Channels in Same Package (ΔRon) | ΔRon | 20 | Ω | VCC = 4.5 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum Difference in ON Resistance Between Any Two Channels in Same Package (ΔRon) | ΔRon | 10 | Ω | VCC = 4.5 V; VEE = −4.5 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; −55 to 25°C | 5 | ||
| Maximum Off-Channel Leakage Current, Any One Channel (Ioff) | Ioff | 0.1 | µA | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off; −55 to 25°C | 5 | ||
| Maximum Off-Channel Leakage Current, Common Channel (VHC4053) | Ioff | 0.1 | µA | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off; −55 to 25°C | 5 | ||
| Maximum On-Channel Leakage Current, Channel-to-Channel (VHC4053) | Ion | 0.1 | µA | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; switch-to-switch = VCC − VEE; −55 to 25°C | 5 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | 270 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | 90 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | 59 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | 45 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | 40 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | 25 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | 12 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | 10 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | 160 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | 70 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | 48 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | 39 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | 245 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | 115 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | 49 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | 39 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 | ||
| Maximum Input Capacitance, Channel-Select or Enable Inputs | Cin | 10 | pF | 6 | |||
| Maximum Capacitance Analog I/O (All Switches Off) | CI/O | 35 | pF | All switches off | 6 |
CAD (KiCad official)
- Symbol:
MC74VHC4053DR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74vhc4053dr2g-etched.step/mc74vhc4053dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74vhc4053dr2g.step/mc74vhc4053dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (19 pp, sha256
4ae2350b8cf5f4c4, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74VHC4053DR2G
**onsemi** · Analog Switches, Multiplexers · SOIC-16
MC74VHC4053DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | passive | Analog input/output of the Y-switch channel Y1; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 2 | Y0 | passive | Analog input/output of the Y-switch channel Y0; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 3 | Z1 | passive | Analog input/output of the Z-switch channel Z1; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 4 | Z | passive | Common output/input of the Z switch; it connects to Z0 or Z1 under control of Channel-Select input C, and analog voltage must stay between VEE and VCC. |
| 5 | Z0 | passive | Analog input/output of the Z-switch channel Z0; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 6 | ENABLE | input | Active-high enable; when HIGH all analog switches are turned off, and the input is CMOS-compatible with a 0 V to VCC logic range (pull-up resistors needed for LSTTL outputs). |
| 7 | VEE | power_in | Negative DC supply for the analog section, which must satisfy VEE − GND = 0 to −6 V and VEE ≤ GND, with VCC − VEE = 2 to 12 V. |
| 8 | GND | power_in | Digital ground reference for the control inputs, with VCC − GND = 2 to 6 V recommended. |
| 9 | C | input | Channel-Select input C that controls the Z switch; it must be driven at VCC or GND logic levels (0 V to VCC). |
| 10 | B | input | Channel-Select input B that controls the Y switch; it must be driven at VCC or GND logic levels (0 V to VCC). |
| 11 | A | input | Channel-Select input A that controls the X switch; it must be driven at VCC or GND logic levels (0 V to VCC). |
| 12 | X0 | passive | Analog input/output of the X-switch channel X0; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 13 | X1 | passive | Analog input/output of the X-switch channel X1; analog voltage must stay between VEE and VCC (maximum rating VEE − 0.5 V to VCC + 0.5 V). |
| 14 | X | passive | Common output/input of the X switch; it connects to X0 or X1 under control of Channel-Select input A, and analog voltage must stay between VEE and VCC. |
| 15 | Y | passive | Common output/input of the Y switch; it connects to Y0 or Y1 under control of Channel-Select input B, and analog voltage must stay between VEE and VCC. |
| 16 | VCC | power_in | Positive DC supply, referenced to GND at 2.0 to 6.0 V and to VEE at 2.0 to 12.0 V (absolute maximum 7.0 V to GND and 14.0 V to VEE). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC Supply Voltage (Referenced to GND) | VCC | -0.5 | | 7 | V | Referenced to GND | 4 |
| Positive DC Supply Voltage (Referenced to VEE) | VCC | -0.5 | | 14 | V | Referenced to VEE | 4 |
| Negative DC Supply Voltage (Referenced to GND) | VEE | -7 | | 5 | V | Referenced to GND | 4 |
| DC Current, Into or Out of Any Pin | I | -25 | | 25 | mA | | 4 |
| Power Dissipation in Still Air, SOIC Package | PD | | | 500 | mW | Still air, SOIC package; derate -7 mW/°C from 65 to 125°C | 4 |
| Storage Temperature Range | Tstg | -65 | | 150 | °C | | 4 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 4 |
| Positive DC Supply Voltage (Referenced to GND) | VCC | 2 | | 6 | V | Referenced to GND | 4 |
| Positive DC Supply Voltage (Referenced to VEE) | VCC | 2 | | 12 | V | Referenced to VEE | 4 |
| Negative DC Supply Voltage, Output (Referenced to GND) | VEE | -6 | | | V | Maximum printed as GND (not a number) | 4 |
| Static or Dynamic Voltage Across Switch | VIO* | | | 1.2 | V | Footnote: above 1.2 V (switch on) excessive VCC current may be drawn | 4 |
| Operating Temperature Range, All Package Types | TA | -55 | | 125 | °C | | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 800 | ns | VCC = 3.0 V | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 500 | ns | VCC = 4.5 V | 4 |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | | 400 | ns | VCC = 6.0 V | 4 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 1.5 | | | V | VCC = 2.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 2.1 | | | V | VCC = 3.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 3.15 | | | V | VCC = 4.5 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 4.2 | | | V | VCC = 6.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 0.5 | V | VCC = 2.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 0.9 | V | VCC = 3.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 1.35 | V | VCC = 4.5 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | | | 1.8 | V | VCC = 6.0 V; VEE = GND; Ron = Per Spec; −55 to 25°C | 5 |
| Maximum Input Leakage Current, Channel-Select or Enable Inputs | Iin | -0.1 | | 0.1 | µA | Vin = VCC or GND; VEE = −6.0 V; VCC = 6.0 V; −55 to 25°C | 5 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 1 | µA | VCC = 6.0 V; VEE = GND; VIS = VCC or GND; VIO = 0 V; −55 to 25°C | 5 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 40 | µA | VCC = 6.0 V; VEE = −6.0 V; VIS = VCC or GND; VIO = 0 V; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron) | Ron | | | 200 | Ω | VCC = 3.0 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron) | Ron | | | 160 | Ω | VCC = 4.5 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron) | Ron | | | 120 | Ω | VCC = 4.5 V; VEE = −4.5 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron) | Ron | | | 100 | Ω | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron), endpoints | Ron | | | 150 | Ω | VCC = 3.0 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron), endpoints | Ron | | | 110 | Ω | VCC = 4.5 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron), endpoints | Ron | | | 90 | Ω | VCC = 4.5 V; VEE = −4.5 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum ON Resistance (Ron), endpoints | Ron | | | 80 | Ω | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum Difference in ON Resistance Between Any Two Channels in Same Package (ΔRon) | ΔRon | | | 40 | Ω | VCC = 3.0 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum Difference in ON Resistance Between Any Two Channels in Same Package (ΔRon) | ΔRon | | | 20 | Ω | VCC = 4.5 V; VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum Difference in ON Resistance Between Any Two Channels in Same Package (ΔRon) | ΔRon | | | 10 | Ω | VCC = 4.5 V; VEE = −4.5 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; −55 to 25°C | 5 |
| Maximum Off-Channel Leakage Current, Any One Channel (Ioff) | Ioff | | | 0.1 | µA | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off; −55 to 25°C | 5 |
| Maximum Off-Channel Leakage Current, Common Channel (VHC4053) | Ioff | | | 0.1 | µA | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off; −55 to 25°C | 5 |
| Maximum On-Channel Leakage Current, Channel-to-Channel (VHC4053) | Ion | | | 0.1 | µA | VCC = 6.0 V; VEE = −6.0 V; Vin = VIL or VIH; switch-to-switch = VCC − VEE; −55 to 25°C | 5 |
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 270 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 90 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 59 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Channel-Select to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 45 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 40 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 25 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 12 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Analog Input to Analog Output (tPLH, tPHL) | tPLH, tPHL | | | 10 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | | | 160 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | | | 70 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | | | 48 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPLZ, tPHZ) | tPLZ, tPHZ | | | 39 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | | | 245 | ns | VCC = 2.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | | | 115 | ns | VCC = 3.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | | | 49 | ns | VCC = 4.5 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Propagation Delay, Enable to Analog Output (tPZL, tPZH) | tPZL, tPZH | | | 39 | ns | VCC = 6.0 V; CL = 50 pF; input tr = tf = 6 ns; −55 to 25°C | 6 |
| Maximum Input Capacitance, Channel-Select or Enable Inputs | Cin | | | 10 | pF | | 6 |
| Maximum Capacitance Analog I/O (All Switches Off) | CI/O | | | 35 | pF | All switches off | 6 |
## CAD (KiCad official)
- Symbol: `MC74VHC4053DR2G`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `mc74vhc4053dr2g-etched.step` / `mc74vhc4053dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74vhc4053dr2g.step` / `mc74vhc4053dr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74vhc4053-d.pdf) (19 pp, sha256 `4ae2350b8cf5f4c4`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74vhc4053dr2g-datasheet.pdf)