component
MC74VHC4052DR2G
Public Made by Adomby adom
onsemi Analog Switches, Multiplexers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MC74VHC4052DR2G
onsemi · Analog Switches, Multiplexers · SOIC-16
MC74VHC4052DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y0 | passive | Analog input/output of the Y-switch channel 0, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 2 | Y2 | passive | Analog input/output of the Y-switch channel 2, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 3 | Y | passive | Common Y analog output/input of the Y switch, connected to the selected Y channel (Y0 to Y3) when Enable is LOW. |
| 4 | Y3 | passive | Analog input/output of the Y-switch channel 3, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 5 | Y1 | passive | Analog input/output of the Y-switch channel 1, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 6 | ENABLE | input | Enable input; when HIGH all analog switches are turned off, and it must be driven to VCC or GND logic levels. |
| 7 | VEE | power_in | Negative DC supply, which must satisfy VEE − GND = 0 to −6.0 V and VEE ≤ GND, giving an analog supply range VCC − VEE of 2.0 to 12.0 V. |
| 8 | GND | power_in | Ground reference for the digital control inputs, with VCC − GND limited to 2.0 to 6.0 V. |
| 9 | B | input | Channel-Select input B, which selects the Y-switch channel together with A and must be driven to VCC or GND logic levels. |
| 10 | A | input | Channel-Select input A, which selects the Y-switch channel together with B and must be driven to VCC or GND logic levels. |
| 11 | X3 | passive | Analog input/output of the X-switch channel 3, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 12 | X0 | passive | Analog input/output of the X-switch channel 0, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 13 | X | passive | Common X analog output/input of the X switch, connected to the selected X channel (X0 to X3) when Enable is LOW. |
| 14 | X1 | passive | Analog input/output of the X-switch channel 1, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 15 | X2 | passive | Analog input/output of the X-switch channel 2, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 16 | VCC | power_in | Positive DC supply, limited to 2.0 to 6.0 V referenced to GND for digital control, and 2.0 to 12.0 V referenced to VEE for the analog section. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC supply voltage (referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 4 | |
| Positive DC supply voltage (referenced to VEE) | VCC | -0.5 | 14 | V | Referenced to VEE | 4 | |
| Negative DC supply voltage (referenced to GND) | VEE | -7 | 5 | V | Referenced to GND | 4 | |
| DC current into or out of any pin | I | -25 | 25 | mA | Into or out of any pin | 4 | |
| Power dissipation in still air, SOIC package | PD | 500 | mW | Still air, SOIC package | 4 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 4 | ||
| Positive DC supply voltage (referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 4 | |
| Positive DC supply voltage (referenced to VEE) | VCC | 2 | 12 | V | Referenced to VEE | 4 | |
| Negative DC supply voltage, output (referenced to GND) | VEE | -6 | V | Referenced to GND; maximum printed as GND | 4 | ||
| Static or dynamic voltage across switch | VIO* | 1.2 | V | 4 | |||
| Operating temperature range, all package types | TA | -55 | 125 | °C | 4 | ||
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 4 | |
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | 800 | ns | VCC = 3.0 V | 4 | |
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 4 | |
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 4 | |
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 1.5 | V | VCC = 2.0 V; Ron = Per Spec | 5 | ||
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 2.1 | V | VCC = 3.0 V; Ron = Per Spec | 5 | ||
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 3.15 | V | VCC = 4.5 V; Ron = Per Spec | 5 | ||
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 4.2 | V | VCC = 6.0 V; Ron = Per Spec | 5 | ||
| Maximum low-level input voltage, channel-select or enable inputs | VIL | 0.5 | V | VCC = 2.0 V; Ron = Per Spec | 5 | ||
| Maximum low-level input voltage, channel-select or enable inputs | VIL | 0.9 | V | VCC = 3.0 V; Ron = Per Spec | 5 | ||
| Maximum low-level input voltage, channel-select or enable inputs | VIL | 1.35 | V | VCC = 4.5 V; Ron = Per Spec | 5 | ||
| Maximum low-level input voltage, channel-select or enable inputs | VIL | 1.8 | V | VCC = 6.0 V; Ron = Per Spec | 5 | ||
| Maximum input leakage current, channel-select or enable inputs | Iin | -1 | 1 | μA | VCC = 6.0 V; Vin = VCC or GND; VEE = -6.0 V; <=125 °C column | 5 | |
| Maximum quiescent supply current (per package) | ICC | 10 | μA | VCC = 6.0 V; channel select, enable and VIS = VCC or GND; VIO = 0 V; VEE = GND; <=125 °C column | 5 | ||
| Maximum quiescent supply current (per package) | ICC | 80 | μA | VCC = 6.0 V; channel select, enable and VIS = VCC or GND; VIO = 0 V; VEE = -6.0 V; <=125 °C column | 5 | ||
| Maximum ON resistance | Ron | 320 | Ω | VCC = 3.0 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum ON resistance | Ron | 280 | Ω | VCC = 4.5 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum ON resistance | Ron | 170 | Ω | VCC = 4.5 V, VEE = -4.5 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum ON resistance | Ron | 140 | Ω | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum ON resistance (endpoints) | Ron | 230 | Ω | VCC = 3.0 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum ON resistance (endpoints) | Ron | 190 | Ω | VCC = 4.5 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum ON resistance (endpoints) | Ron | 140 | Ω | VCC = 4.5 V, VEE = -4.5 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum ON resistance (endpoints) | Ron | 115 | Ω | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | 80 | Ω | VCC = 3.0 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | 40 | Ω | VCC = 4.5 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | 18 | Ω | VCC = 4.5 V, VEE = -4.5 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | 14 | Ω | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 | ||
| Maximum off-channel leakage current, any one channel | Ioff | 1 | μA | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off (Figure 12); <=125 °C column | 5 | ||
| Maximum off-channel leakage current, common channel (VHC4052) | Ioff | 2 | μA | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off (Figure 13); <=125 °C column | 5 | ||
| Maximum on-channel leakage current, channel-to-channel (VHC4052) | Ion | 2 | μA | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; switch-to-switch = VCC − VEE (Figure 14); <=125 °C column | 5 | ||
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | 350 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | 125 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | 85 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 | ||
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | 75 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | 70 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | 32 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | 18 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 | ||
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | 15 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | 220 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | 110 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | 76 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | 63 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | 345 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | 155 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | 83 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 | ||
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | 67 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 | ||
| Maximum input capacitance, channel-select or enable inputs | Cin | 10 | pF | 6 | |||
| Maximum capacitance, common O/I (VHC4052), all switches off | CI/O | 80 | pF | All switches off | 6 |
CAD (KiCad official)
- Symbol:
MC74VHC4052DR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74vhc4052dr2g-etched.step/mc74vhc4052dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74vhc4052dr2g.step/mc74vhc4052dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (19 pp, sha256
4ae2350b8cf5f4c4, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74VHC4052DR2G
**onsemi** · Analog Switches, Multiplexers · SOIC-16
MC74VHC4052DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y0 | passive | Analog input/output of the Y-switch channel 0, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 2 | Y2 | passive | Analog input/output of the Y-switch channel 2, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 3 | Y | passive | Common Y analog output/input of the Y switch, connected to the selected Y channel (Y0 to Y3) when Enable is LOW. |
| 4 | Y3 | passive | Analog input/output of the Y-switch channel 3, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 5 | Y1 | passive | Analog input/output of the Y-switch channel 1, connected to Common Y when selected by Channel-Select inputs A and B; signals should stay within GND to VCC for proper operation. |
| 6 | ENABLE | input | Enable input; when HIGH all analog switches are turned off, and it must be driven to VCC or GND logic levels. |
| 7 | VEE | power_in | Negative DC supply, which must satisfy VEE − GND = 0 to −6.0 V and VEE ≤ GND, giving an analog supply range VCC − VEE of 2.0 to 12.0 V. |
| 8 | GND | power_in | Ground reference for the digital control inputs, with VCC − GND limited to 2.0 to 6.0 V. |
| 9 | B | input | Channel-Select input B, which selects the Y-switch channel together with A and must be driven to VCC or GND logic levels. |
| 10 | A | input | Channel-Select input A, which selects the Y-switch channel together with B and must be driven to VCC or GND logic levels. |
| 11 | X3 | passive | Analog input/output of the X-switch channel 3, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 12 | X0 | passive | Analog input/output of the X-switch channel 0, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 13 | X | passive | Common X analog output/input of the X switch, connected to the selected X channel (X0 to X3) when Enable is LOW. |
| 14 | X1 | passive | Analog input/output of the X-switch channel 1, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 15 | X2 | passive | Analog input/output of the X-switch channel 2, connected to Common X when selected by the Enable and Channel-Select inputs. |
| 16 | VCC | power_in | Positive DC supply, limited to 2.0 to 6.0 V referenced to GND for digital control, and 2.0 to 12.0 V referenced to VEE for the analog section. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC supply voltage (referenced to GND) | VCC | -0.5 | | 7 | V | Referenced to GND | 4 |
| Positive DC supply voltage (referenced to VEE) | VCC | -0.5 | | 14 | V | Referenced to VEE | 4 |
| Negative DC supply voltage (referenced to GND) | VEE | -7 | | 5 | V | Referenced to GND | 4 |
| DC current into or out of any pin | I | -25 | | 25 | mA | Into or out of any pin | 4 |
| Power dissipation in still air, SOIC package | PD | | | 500 | mW | Still air, SOIC package | 4 |
| Storage temperature range | Tstg | -65 | | 150 | °C | | 4 |
| Lead temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 4 |
| Positive DC supply voltage (referenced to GND) | VCC | 2 | | 6 | V | Referenced to GND | 4 |
| Positive DC supply voltage (referenced to VEE) | VCC | 2 | | 12 | V | Referenced to VEE | 4 |
| Negative DC supply voltage, output (referenced to GND) | VEE | -6 | | | V | Referenced to GND; maximum printed as GND | 4 |
| Static or dynamic voltage across switch | VIO* | | | 1.2 | V | | 4 |
| Operating temperature range, all package types | TA | -55 | | 125 | °C | | 4 |
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V | 4 |
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | | 800 | ns | VCC = 3.0 V | 4 |
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | | 500 | ns | VCC = 4.5 V | 4 |
| Input rise/fall time (channel select or enable inputs) | tr, tf | 0 | | 400 | ns | VCC = 6.0 V | 4 |
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 1.5 | | | V | VCC = 2.0 V; Ron = Per Spec | 5 |
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 2.1 | | | V | VCC = 3.0 V; Ron = Per Spec | 5 |
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 3.15 | | | V | VCC = 4.5 V; Ron = Per Spec | 5 |
| Minimum high-level input voltage, channel-select or enable inputs | VIH | 4.2 | | | V | VCC = 6.0 V; Ron = Per Spec | 5 |
| Maximum low-level input voltage, channel-select or enable inputs | VIL | | | 0.5 | V | VCC = 2.0 V; Ron = Per Spec | 5 |
| Maximum low-level input voltage, channel-select or enable inputs | VIL | | | 0.9 | V | VCC = 3.0 V; Ron = Per Spec | 5 |
| Maximum low-level input voltage, channel-select or enable inputs | VIL | | | 1.35 | V | VCC = 4.5 V; Ron = Per Spec | 5 |
| Maximum low-level input voltage, channel-select or enable inputs | VIL | | | 1.8 | V | VCC = 6.0 V; Ron = Per Spec | 5 |
| Maximum input leakage current, channel-select or enable inputs | Iin | -1 | | 1 | μA | VCC = 6.0 V; Vin = VCC or GND; VEE = -6.0 V; <=125 °C column | 5 |
| Maximum quiescent supply current (per package) | ICC | | | 10 | μA | VCC = 6.0 V; channel select, enable and VIS = VCC or GND; VIO = 0 V; VEE = GND; <=125 °C column | 5 |
| Maximum quiescent supply current (per package) | ICC | | | 80 | μA | VCC = 6.0 V; channel select, enable and VIS = VCC or GND; VIO = 0 V; VEE = -6.0 V; <=125 °C column | 5 |
| Maximum ON resistance | Ron | | | 320 | Ω | VCC = 3.0 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum ON resistance | Ron | | | 280 | Ω | VCC = 4.5 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum ON resistance | Ron | | | 170 | Ω | VCC = 4.5 V, VEE = -4.5 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum ON resistance | Ron | | | 140 | Ω | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIS = VCC to VEE; IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum ON resistance (endpoints) | Ron | | | 230 | Ω | VCC = 3.0 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum ON resistance (endpoints) | Ron | | | 190 | Ω | VCC = 4.5 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum ON resistance (endpoints) | Ron | | | 140 | Ω | VCC = 4.5 V, VEE = -4.5 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum ON resistance (endpoints) | Ron | | | 115 | Ω | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIS = VCC or VEE (endpoints); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | | | 80 | Ω | VCC = 3.0 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | | | 40 | Ω | VCC = 4.5 V, VEE = 0.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | | | 18 | Ω | VCC = 4.5 V, VEE = -4.5 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum difference in ON resistance between any two channels in the same package | ΔRon | | | 14 | Ω | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA; <=125 °C column | 5 |
| Maximum off-channel leakage current, any one channel | Ioff | | | 1 | μA | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off (Figure 12); <=125 °C column | 5 |
| Maximum off-channel leakage current, common channel (VHC4052) | Ioff | | | 2 | μA | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; VIO = VCC − VEE; switch off (Figure 13); <=125 °C column | 5 |
| Maximum on-channel leakage current, channel-to-channel (VHC4052) | Ion | | | 2 | μA | VCC = 6.0 V, VEE = -6.0 V; Vin = VIL or VIH; switch-to-switch = VCC − VEE (Figure 14); <=125 °C column | 5 |
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | | | 350 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 |
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | | | 125 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 |
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | | | 85 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 |
| Maximum propagation delay, channel select to analog output | tPLH, tPHL | | | 75 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 |
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | | | 70 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 |
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | | | 32 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 |
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | | | 18 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 |
| Maximum propagation delay, analog input to analog output | tPLH, tPHL | | | 15 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | | | 220 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | | | 110 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | | | 76 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output | tPLZ, tPHZ | | | 63 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | | | 345 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 2.0 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | | | 155 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 3.0 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | | | 83 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 4.5 V; <=125 °C column | 6 |
| Maximum propagation delay, enable to analog output (turn-on) | tPZL, tPZH | | | 67 | ns | CL = 50 pF, input tr = tf = 6 ns; VCC = 6.0 V; <=125 °C column | 6 |
| Maximum input capacitance, channel-select or enable inputs | Cin | | | 10 | pF | | 6 |
| Maximum capacitance, common O/I (VHC4052), all switches off | CI/O | | | 80 | pF | All switches off | 6 |
## CAD (KiCad official)
- Symbol: `MC74VHC4052DR2G`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `mc74vhc4052dr2g-etched.step` / `mc74vhc4052dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74vhc4052dr2g.step` / `mc74vhc4052dr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74vhc4052-d.pdf) (19 pp, sha256 `4ae2350b8cf5f4c4`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74vhc4052dr2g-datasheet.pdf)