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MC74VHC132DG

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onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74VHC132DG

onsemi · Logic Gates · SOIC-14

MC74VHC132DG from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input A of NAND gate 1; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and DC input voltage must stay between GND and VCC for proper operation.
2 B1 input Input B of NAND gate 1; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and unused inputs must be tied to GND or VCC.
3 Y1 output Output of NAND gate 1 (Y = NOT(A AND B)); absolute maximum DC output current is 25 mA per pin, and unused outputs must be left open.
4 A2 input Input A of NAND gate 2; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and DC input voltage must stay between GND and VCC for proper operation.
5 B2 input Input B of NAND gate 2; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and unused inputs must be tied to GND or VCC.
6 Y2 output Output of NAND gate 2 (Y = NOT(A AND B)); absolute maximum DC output current is 25 mA per pin, and unused outputs must be left open.
7 GND power_in Ground reference; Vin and Vout must be constrained to the range GND to VCC.
8 Y3 output Output of NAND gate 3 (Y = NOT(A AND B)); absolute maximum DC output current is 25 mA per pin, and unused outputs must be left open.
9 A3 input Input A of NAND gate 3; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and DC input voltage must stay between GND and VCC for proper operation.
10 B3 input Input B of NAND gate 3; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and unused inputs must be tied to GND or VCC.
11 Y4 output Output of NAND gate 4 (Y = NOT(A AND B)); absolute maximum DC output current is 25 mA per pin, and unused outputs must be left open.
12 A4 input Input A of NAND gate 4; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and DC input voltage must stay between GND and VCC for proper operation.
13 B4 input Input B of NAND gate 4; a Schmitt-trigger input with hysteresis that tolerates voltages up to 7.0 V, and unused inputs must be tied to GND or VCC.
14 VCC power_in Positive supply; the device is designed for a 2.0 V to 5.5 V operating range.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive Threshold Voltage VT+ 2.2 V VCC = 3.0 V; TA = 25°C; Figure 5 3
Positive Threshold Voltage VT+ 3.15 V VCC = 4.5 V; TA = 25°C; Figure 5 3
Positive Threshold Voltage VT+ 3.85 V VCC = 5.5 V; TA = 25°C; Figure 5 3
Negative Threshold Voltage VT− 0.9 V VCC = 3.0 V; TA = 25°C; Figure 5 3
Negative Threshold Voltage VT− 1.35 V VCC = 4.5 V; TA = 25°C; Figure 5 3
Negative Threshold Voltage VT− 1.65 V VCC = 5.5 V; TA = 25°C; Figure 5 3
Minimum High-Level Output Voltage VOH 1.9 V Vin = VIH or VIL; IOH = −50 µA; VCC = 2.0 V; TA = −55 to +125°C 3
Minimum High-Level Output Voltage VOH 2.9 V Vin = VIH or VIL; IOH = −50 µA; VCC = 3.0 V; TA = −55 to +125°C 3
Minimum High-Level Output Voltage VOH 4.4 V Vin = VIH or VIL; IOH = −50 µA; VCC = 4.5 V; TA = −55 to +125°C 3
Minimum High-Level Output Voltage VOH 2.58 V Vin = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA = 25°C 3
Minimum High-Level Output Voltage VOH 2.48 V Vin = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA = −55 to +125°C 3
Minimum High-Level Output Voltage VOH 3.94 V Vin = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA = 25°C 3
Minimum High-Level Output Voltage VOH 3.8 V Vin = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA = −55 to +125°C 3
Maximum Low-Level Output Voltage VOL 0.1 V Vin = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = 25°C 3
Maximum Low-Level Output Voltage VOL 0.36 V Vin = VIH or VIL; IOL = 4 mA; VCC = 3.0 V; TA = 25°C 3
Maximum Low-Level Output Voltage VOL 0.44 V Vin = VIH or VIL; IOL = 4 mA; VCC = 3.0 V; TA = −55 to +125°C 3
Maximum Input Leakage Current Iin -0.1 0.1 µA Vin = 5.5 V or GND; VCC = 0 to 5.5 V; TA = 25°C 3
Maximum Input Leakage Current Iin -1 1 µA Vin = 5.5 V or GND; VCC = 0 to 5.5 V; TA = −55 to +125°C 3
Maximum Quiescent Supply Current ICC 2 µA Vin = VCC or GND; VCC = 5.5 V; TA = 25°C 3
Maximum Quiescent Supply Current ICC 20 µA Vin = VCC or GND; VCC = 5.5 V; TA = −55 to +125°C 3
Maximum Input Capacitance Cin 4 10 pF TA = 25°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 1 7.6 11.9 ns VCC = 3.3 ± 0.3 V; CL = 15 pF; TA = 25°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 1 10.1 15.4 ns VCC = 3.3 ± 0.3 V; CL = 50 pF; TA = 25°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 14 ns VCC = 3.3 ± 0.3 V; CL = 15 pF; TA = −55 to +125°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 17.5 ns VCC = 3.3 ± 0.3 V; CL = 50 pF; TA = −55 to +125°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 1 4.9 7.7 ns VCC = 5.0 ± 0.5 V; CL = 15 pF; TA = 25°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 1 6.4 9.7 ns VCC = 5.0 ± 0.5 V; CL = 50 pF; TA = 25°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 9 ns VCC = 5.0 ± 0.5 V; CL = 15 pF; TA = −55 to +125°C 3
Maximum Propagation Delay, A or B to Y tPLH, tPHL 11 ns VCC = 5.0 ± 0.5 V; CL = 50 pF; TA = −55 to +125°C 3
Quiet Output Maximum Dynamic VOL VOLP 0.3 0.8 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 3
Quiet Output Minimum Dynamic VOL VOLV -0.3 -0.8 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 3
Minimum High Level Dynamic Input Voltage VIHD 3.5 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 3
Maximum Low Level Dynamic Input Voltage VILD 1.5 V Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C 3
DC Supply Voltage VCC 2 5.5 V 2
DC Input Voltage Vin 0 5.5 V 2
DC Output Voltage Vout 0 V max = VCC 2
Operating Temperature, All Package Types TA -55 125 °C 2
DC Supply Voltage VCC -0.5 7 V 2
DC Input Voltage Vin -0.5 7 V 2
DC Output Voltage Vout -0.5 V max = VCC +0.5 2
Input Diode Current IIK -20 mA 2
Output Diode Current IOK 20 mA 2
DC Output Current, per Pin Iout 25 mA 2
DC Supply Current, VCC and GND Pins ICC 50 mA 2
Power Dissipation in Still Air, SOIC Packages PD 500 mW SOIC package; still air 2
Storage Temperature Tstg -65 150 °C 2

CAD (KiCad official)

  • Symbol: MC74VHC132DG
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74vhc132dg-etched.step / mc74vhc132dg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74vhc132dg.step / mc74vhc132dg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 6974634056b603f9, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF