# MC74VHC08DTR2G

**onsemi** · Logic Gates · TSSOP-14

MC74VHC08DTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A of AND gate 1; the inputs tolerate voltages up to 7.0 V. |
| 2 | B1 | input | Input B of AND gate 1; the inputs tolerate voltages up to 7.0 V. |
| 3 | Y1 | output | Output of AND gate 1, where Y = A·B. |
| 4 | A2 | input | Input A of AND gate 2; the inputs tolerate voltages up to 7.0 V. |
| 5 | B2 | input | Input B of AND gate 2; the inputs tolerate voltages up to 7.0 V. |
| 6 | Y2 | output | Output of AND gate 2, where Y = A·B. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | Y3 | output | Output of AND gate 3, where Y = A·B. |
| 9 | A3 | input | Input A of AND gate 3; the inputs tolerate voltages up to 7.0 V. |
| 10 | B3 | input | Input B of AND gate 3; the inputs tolerate voltages up to 7.0 V. |
| 11 | Y4 | output | Output of AND gate 4, where Y = A·B. |
| 12 | A4 | input | Input A of AND gate 4; the inputs tolerate voltages up to 7.0 V. |
| 13 | B4 | input | Input B of AND gate 4; the inputs tolerate voltages up to 7.0 V. |
| 14 | VCC | power_in | Positive supply pin; the device is designed for a 2.0 V to 5.5 V operating range. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | 2 |  | 5.5 | V |  | 2 |
| DC Input Voltage | Vin | 0 |  | 5.5 | V |  | 2 |
| DC Output Voltage | Vout | 0 |  |  | V |  | 2 |
| Operating Temperature | TA | -55 |  | 125 | °C |  | 2 |
| Input Rise and Fall Time | tr, tf | 0 |  | 100 | ns/V | VCC = 3.3 V ±0.3 V | 2 |
| Input Rise and Fall Time | tr, tf | 0 |  | 20 | ns/V | VCC = 5.0 V ±0.5 V | 2 |
| DC Supply Voltage | VCC | -0.5 |  | 7 | V |  | 2 |
| DC Input Voltage | Vin | -0.5 |  | 7 | V |  | 2 |
| DC Output Voltage | Vout | -0.5 |  |  | V |  | 2 |
| Input Diode Current | IIK |  |  | -20 | mA |  | 2 |
| Output Diode Current | IOK | -20 |  | 20 | mA |  | 2 |
| DC Output Current, per Pin | Iout | -25 |  | 25 | mA |  | 2 |
| DC Supply Current, VCC and GND Pins | ICC | -50 |  | 50 | mA |  | 2 |
| Power Dissipation in Still Air, TSSOP Package | PD |  |  | 450 | mW | TSSOP package, still air | 2 |
| Storage Temperature | Tstg | -65 |  | 150 | °C |  | 2 |
| Minimum High-Level Input Voltage | VIH | 1.5 |  |  | V | VCC = 2.0 V; TA = 25°C | 2 |
| Maximum Low-Level Input Voltage | VIL |  |  | 0.5 | V | VCC = 2.0 V; TA = 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 1.9 | 2 |  | V | Vin = VIH or VIL; IOH = -50 µA; VCC = 2.0 V; TA = 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 2.9 | 3 |  | V | Vin = VIH or VIL; IOH = -50 µA; VCC = 3.0 V; TA = 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 4.4 | 4.5 |  | V | Vin = VIH or VIL; IOH = -50 µA; VCC = 4.5 V; TA = 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 2.58 |  |  | V | Vin = VIH or VIL; IOH = -4.0 mA; VCC = 3.0 V; TA = 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 2.48 |  |  | V | Vin = VIH or VIL; IOH = -4.0 mA; VCC = 3.0 V; TA = -55°C to 125°C | 2 |
| Minimum High-Level Output Voltage | VOH | 3.94 |  |  | V | Vin = VIH or VIL; IOH = -8.0 mA; VCC = 4.5 V; TA = 25°C | 2 |
| Minimum High-Level Output Voltage | VOH | 3.8 |  |  | V | Vin = VIH or VIL; IOH = -8.0 mA; VCC = 4.5 V; TA = -55°C to 125°C | 2 |
| Maximum Low-Level Output Voltage | VOL |  | 0 | 0.1 | V | Vin = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = 25°C | 2 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.1 | V | Vin = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = -55°C to 125°C | 2 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.36 | V | Vin = VIH or VIL; IOL = 4.0 mA; VCC = 3.0 V; TA = 25°C | 2 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.44 | V | Vin = VIH or VIL; IOL = 4.0 mA; VCC = 3.0 V; TA = -55°C to 125°C | 2 |
| Maximum Input Leakage Current | Iin | -0.1 |  | 0.1 | A | Vin = 5.5 V or GND; VCC = 0 to 5.5 V; TA = 25°C | 2 |
| Maximum Input Leakage Current | Iin | -1 |  | 1 | A | Vin = 5.5 V or GND; VCC = 0 to 5.5 V; TA = -55°C to 125°C | 2 |
| Maximum Quiescent Supply Current | ICC |  |  | 2 | A | Vin = VCC or GND; VCC = 5.5 V; TA = 25°C | 2 |
| Maximum Quiescent Supply Current | ICC |  |  | 20 | A | Vin = VCC or GND; VCC = 5.5 V; TA = -55°C to 125°C | 2 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 | 6.2 | 8.7 | ns | VCC = 3.3 ± 0.3 V; CL = 15 pF; TA = 25°C; tr = tf = 3.0 ns | 3 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 |  | 10.5 | ns | VCC = 3.3 ± 0.3 V; CL = 15 pF; TA = -55°C to 125°C; tr = tf = 3.0 ns | 3 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 | 8.8 | 12.3 | ns | VCC = 3.3 ± 0.3 V; CL = 50 pF; TA = 25°C; tr = tf = 3.0 ns | 3 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 |  | 14 | ns | VCC = 3.3 ± 0.3 V; CL = 50 pF; TA = -55°C to 125°C; tr = tf = 3.0 ns | 3 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 | 4.3 | 5.8 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; TA = 25°C; tr = tf = 3.0 ns | 3 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 |  | 7 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; TA = -55°C to 125°C; tr = tf = 3.0 ns | 3 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 | 5.9 | 7.9 | ns | VCC = 5.0 ± 0.5 V; CL = 50 pF; TA = 25°C; tr = tf = 3.0 ns | 3 |
| Maximum Propagation Delay, A or B to Y | tPLH, tPHL | 1 |  | 9 | ns | VCC = 5.0 ± 0.5 V; CL = 50 pF; TA = -55°C to 125°C; tr = tf = 3.0 ns | 3 |
| Maximum Input Capacitance | Cin |  | 4 | 10 | pF | TA = 25°C | 3 |
| Maximum Input Capacitance | Cin |  |  | 10 | pF | TA = -55°C to 125°C | 3 |
| Quiet Output Maximum Dynamic VOL | VOLP |  | 0.3 | 0.8 | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 3 |
| Quiet Output Minimum Dynamic VOL | VOLV |  | -0.3 | -0.8 | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 3 |
| Minimum High Level Dynamic Input Voltage | VIHD | 3.5 |  |  | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 3 |
| Maximum Low Level Dynamic Input Voltage | VILD |  |  | 1.5 | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 3 |

## CAD (KiCad official)

- Symbol: `MC74VHC08DTR2G`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `mc74vhc08dtr2g-etched.step` / `mc74vhc08dtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74vhc08dtr2g.step` / `mc74vhc08dtr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74vhc08dtr2-d.pdf) (7 pp, sha256 `d9a731524410f554`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mc74vhc08dtr2g-datasheet.pdf)