component
MC74LVX8053DR2G
Public Made by Adomby adom
onsemi Analog Switches, Multiplexers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74LVX8053DR2G
onsemi · Analog Switches, Multiplexers · SOIC-16
MC74LVX8053DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | passive | Analog input/output position 1 of the Y switch; analog voltages must stay between GND and VCC. |
| 2 | Y0 | passive | Analog input/output position 0 of the Y switch; analog voltages must stay between GND and VCC. |
| 3 | Z1 | passive | Analog input/output position 1 of the Z switch; analog voltages must stay between GND and VCC. |
| 4 | Z | passive | Common analog output/input of the Z switch, connected to Z0 or Z1 as selected by input C. |
| 5 | Z0 | passive | Analog input/output position 0 of the Z switch; analog voltages must stay between GND and VCC. |
| 6 | ENABLE | input | Active-high disable input; when HIGH all analog switches are turned off, and it must be held at GND or VCC (Vin range GND to VCC). |
| 7 | NC | unconnected | Labeled NC in the pin assignment; the datasheet specifies no internal function for this pin. |
| 8 | GND | power_in | Ground reference (0 V) for all voltages; VCC must be 2.5 V to 6.0 V above GND. |
| 9 | C | input | Channel-select input controlling the Z switch; must be held at VCC or GND logic levels. |
| 10 | B | input | Channel-select input controlling the Y switch; must be held at VCC or GND logic levels. |
| 11 | A | input | Channel-select input controlling the X switch; must be held at VCC or GND logic levels. |
| 12 | X0 | passive | Analog input/output position 0 of the X switch; analog voltages must stay between GND and VCC. |
| 13 | X1 | passive | Analog input/output position 1 of the X switch; analog voltages must stay between GND and VCC. |
| 14 | X | passive | Common analog output/input of the X switch, connected to X0 or X1 as selected by input A. |
| 15 | Y | passive | Common analog output/input of the Y switch, connected to Y0 or Y1 as selected by input B. |
| 16 | VCC | power_in | Positive supply, 2.5 V to 6.0 V referenced to GND (absolute maximum +7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC Supply Voltage (Referenced to GND) | VCC | 2.5 | 6 | V | Referenced to GND | 2 | |
| Analog Input Voltage | VIS | 0 | V | 2 | |||
| Static or Dynamic Voltage Across Switch | VIO | 1.2 | V | 2 | |||
| Operating Temperature Range | TA | -55 | 85 | °C | All package types | 2 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 100 | ns/V | VCC = 3.3 V ± 0.3 V | 2 | |
| Input Rise/Fall Time (Channel Select or Enable Inputs) | tr, tf | 0 | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 2 | |
| Positive DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| Analog Input Voltage | VIS | -0.5 | V | 2 | |||
| Digital Input Voltage (Referenced to GND) | Vin | -0.5 | V | Referenced to GND | 2 | ||
| DC Current, Into or Out of Any Pin | I | -20 | 20 | mA | 2 | ||
| Power Dissipation in Still Air | PD | 500 | mW | SOIC package | 2 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 1.5 | V | VCC = 2.5 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 2.1 | V | VCC = 3.0 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 3.15 | V | VCC = 4.5 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Minimum High-Level Input Voltage, Channel-Select or Enable Inputs | VIH | 3.85 | V | VCC = 5.5 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 0.5 | V | VCC = 2.5 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 0.9 | V | VCC = 3.0 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 1.35 | V | VCC = 4.5 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs | VIL | 1.65 | V | VCC = 5.5 V; Ron = Per Spec; −55 to 125°C | 3 | ||
| Maximum Input Leakage Current, Channel-Select or Enable Inputs | Iin | -1 | 1 | µA | VCC = 5.5 V; Vin = VCC or GND; ≤125°C | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | VCC = 5.5 V; Channel Select, Enable and VIS = VCC or GND; VIO = 0 V; ≤125°C | 3 | ||
| Maximum ON Resistance (Ron) | Ron | 50 | Ω | VCC = 3.0 V; Vin = VIL or VIH; VIS = VCC to GND; /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum ON Resistance (Ron) | Ron | 37 | Ω | VCC = 4.5 V; Vin = VIL or VIH; VIS = VCC to GND; /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum ON Resistance (Ron) | Ron | 30 | Ω | VCC = 5.5 V; Vin = VIL or VIH; VIS = VCC to GND; /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum ON Resistance at Endpoints (Ron) | Ron | 40 | Ω | VCC = 3.0 V; Vin = VIL or VIH; VIS = VCC or GND (endpoints); /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum ON Resistance at Endpoints (Ron) | Ron | 35 | Ω | VCC = 4.5 V; Vin = VIL or VIH; VIS = VCC or GND (endpoints); /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum ON Resistance at Endpoints (Ron) | Ron | 30 | Ω | VCC = 5.5 V; Vin = VIL or VIH; VIS = VCC or GND (endpoints); /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum Difference in ON Resistance Between Any Two Channels in the Same Package | Ron | 25 | Ω | VCC = 3.0 V; Vin = VIL or VIH; VIS = 1/2 (VCC − GND); /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum Difference in ON Resistance Between Any Two Channels in the Same Package | Ron | 15 | Ω | VCC = 4.5 V; Vin = VIL or VIH; VIS = 1/2 (VCC − GND); /IS/ ≤ 10.0 mA; ≤125°C | 3 | ||
| Maximum Off-Channel Leakage Current, Any One Channel | Ioff | 1 | µA | VCC = 5.5 V; Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 3); ≤125°C | 3 | ||
| Maximum Off-Channel Leakage Current, Common Channel | Ioff | 2 | µA | VCC = 5.5 V; Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4); ≤125°C | 3 | ||
| Maximum On-Channel Leakage Current, Channel-to-Channel | Ion | 2 | µA | VCC = 5.5 V; Vin = VIL or VIH; Switch-to-Switch = VCC or GND (Figure 5); ≤125°C | 3 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 40 | ns | VCC = 2.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 9; ≤125°C | 4 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 30 | ns | VCC = 3.0 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 9; ≤125°C | 4 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 22 | ns | VCC = 4.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 9; ≤125°C | 4 | ||
| Maximum Propagation Delay, Channel-Select to Analog Output | tPLH, tPHL | 20 | ns | VCC = 5.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 9; ≤125°C | 4 | ||
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | 8 | ns | VCC = 2.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 10; ≤125°C | 4 | ||
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | 6 | ns | VCC = 3.0 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 10; ≤125°C | 4 | ||
| Maximum Propagation Delay, Analog Input to Analog Output | tPLH, tPHL | 2 | ns | VCC = 4.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 10; ≤125°C | 4 | ||
| Maximum Propagation Delay, Enable to Analog Output (disable) | tPLZ, tPHZ | 40 | ns | VCC = 2.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 11; ≤125°C | 4 | ||
| Maximum Propagation Delay, Enable to Analog Output (disable) | tPLZ, tPHZ | 30 | ns | VCC = 3.0 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 11; ≤125°C | 4 | ||
| Maximum Propagation Delay, Enable to Analog Output (disable) | tPLZ, tPHZ | 22 | ns | VCC = 4.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 11; ≤125°C | 4 | ||
| Maximum Propagation Delay, Enable to Analog Output (disable) | tPLZ, tPHZ | 20 | ns | VCC = 5.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 11; ≤125°C | 4 | ||
| Maximum Propagation Delay, Enable to Analog Output (enable) | tPZL, tPZH | 30 | ns | VCC = 2.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 11; ≤125°C | 4 | ||
| Maximum Propagation Delay, Enable to Analog Output (enable) | tPZL, tPZH | 15 | ns | VCC = 3.0 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 11; ≤125°C | 4 | ||
| Maximum Propagation Delay, Enable to Analog Output (enable) | tPZL, tPZH | 12 | ns | VCC = 4.5 V; CL = 50 pF; Input tr = tf = 3 ns; Figure 11; ≤125°C | 4 | ||
| Maximum Input Capacitance, Channel-Select or Enable Inputs | Cin | 10 | pF | 4 | |||
| Maximum Capacitance, Analog I/O | CI/O | 35 | pF | All Switches Off | 4 | ||
| Maximum Capacitance, Common O/I | CI/O | 50 | pF | All Switches Off | 4 | ||
| Maximum Capacitance, Feedthrough | CI/O | 1 | pF | All Switches Off | 4 | ||
| Total Harmonic Distortion (THD) | THD | 0.1 | % | VCC = 3.0 V; fin = 1 kHz; RL = 10k, CL = 50pF; VIS = 2.0 VPP sine wave | 4 | ||
| Total Harmonic Distortion (THD) | THD | 0.08 | % | VCC = 4.5 V; fin = 1 kHz; RL = 10k, CL = 50pF; VIS = 4.0 VPP sine wave | 4 | ||
| Total Harmonic Distortion (THD) | THD | 0.05 | % | VCC = 5.5 V; fin = 1 kHz; RL = 10k, CL = 50pF; VIS = 5.5 VPP sine wave | 4 |
CAD (KiCad official)
- Symbol:
MC74LVX8053DR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74lvx8053dr2g-etched.step/mc74lvx8053dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74lvx8053dr2g.step/mc74lvx8053dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
50d7e40331b10910, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).