component

MC74LVX125DR2G

Public Made by Adom

by adom

onsemi Buffers, Drivers, Receivers, Transceivers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicmc74lvx125dr2gfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

MC74LVX125DR2G

onsemi · Buffers, Drivers, Receivers, Transceivers · SOIC-14

MC74LVX125DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE0 input Output enable input for buffer 0; driving it High places O0 in the high-impedance state, and it must not be left floating.
2 D0 input Data input for buffer 0; absolute maximum is 6.5 V and recommended input range is 0 V to 5.5 V.
3 O0 tri_state 3-state output of buffer 0; DC output current is limited to ±25 mA per pin.
4 OE1 input Output enable input for buffer 1; driving it High places O1 in the high-impedance state, and it must not be left floating.
5 D1 input Data input for buffer 1; absolute maximum is 6.5 V and recommended input range is 0 V to 5.5 V.
6 O1 tri_state 3-state output of buffer 1; DC output current is limited to ±25 mA per pin.
7 GND power_in Ground reference pin; the datasheet gives only the ±50 mA DC limit for the combined VCC and GND pins.
8 O2 tri_state 3-state output of buffer 2; DC output current is limited to ±25 mA per pin.
9 D2 input Data input for buffer 2; absolute maximum is 6.5 V and recommended input range is 0 V to 5.5 V.
10 OE2 input Output enable input for buffer 2; driving it High places O2 in the high-impedance state, and it must not be left floating.
11 O3 tri_state 3-state output of buffer 3; DC output current is limited to ±25 mA per pin.
12 D3 input Data input for buffer 3; absolute maximum is 6.5 V and recommended input range is 0 V to 5.5 V.
13 OE3 input Output enable input for buffer 3; driving it High places O3 in the high-impedance state, and it must not be left floating.
14 VCC power_in Positive supply pin; recommended operating range is 2.0 V to 3.6 V, with absolute maximum of −0.5 V to +6.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 6.5 V 2
DC Input Voltage Vin -0.5 6.5 V 2
Input Diode Current IIK -20 mA 2
Output Diode Current IOK -20 20 mA 2
DC Output Current, per Pin Iout -25 25 mA 2
DC Supply Current, VCC and GND Pins ICC -50 50 mA 2
Power Dissipation PD 1077 mW SOIC-14 NB 2
DC Supply Voltage VCC 2 3.6 V 2
DC Input Voltage Vin 0 5.5 V 2
Operating Temperature, All Package Types TA -40 85 °C 2
High-Level Input Voltage VIH 1.5 V VCC = 2.0 V, TA = 25 °C 2
High-Level Input Voltage VIH 2 V VCC = 3.0 V, TA = 25 °C 2
High-Level Input Voltage VIH 2.4 V VCC = 3.6 V, TA = 25 °C 2
Low-Level Input Voltage VIL 0.5 V VCC = 2.0 V, TA = 25 °C 2
Low-Level Input Voltage VIL 0.8 V VCC = 3.0 V, TA = 25 °C 2
High-Level Output Voltage VOH 1.9 V VCC = 2.0 V, IOH = −50 µA, Vin = VIH or VIL, TA = 25 °C 2
High-Level Output Voltage VOH 2.9 V VCC = 3.0 V, IOH = −50 µA, Vin = VIH or VIL, TA = 25 °C 2
High-Level Output Voltage VOH 2.58 V VCC = 3.0 V, IOH = −4 mA, Vin = VIH or VIL, TA = 25 °C 2
High-Level Output Voltage VOH 2.48 V VCC = 3.0 V, IOH = −4 mA, Vin = VIH or VIL, TA = −40 to 85 °C 2
Low-Level Output Voltage VOL 0 0.1 V VCC = 2.0 V, IOL = 50 µA, Vin = VIH or VIL, TA = 25 °C 2
Low-Level Output Voltage VOL 0.1 V VCC = 2.0 V, IOL = 50 µA, Vin = VIH or VIL, TA = −40 to 85 °C 2
Low-Level Output Voltage VOL 0.36 V VCC = 3.0 V, IOL = 4 mA, Vin = VIH or VIL, TA = 25 °C 2
Low-Level Output Voltage VOL 0.44 V VCC = 3.0 V, IOL = 4 mA, Vin = VIH or VIL, TA = −40 to 85 °C 2
Input Leakage Current Iin -0.1 0.1 µA VCC = 3.6 V, Vin = 5.5 V or GND, TA = 25 °C 2
Input Leakage Current Iin -1 1 µA VCC = 3.6 V, Vin = 5.5 V or GND, TA = −40 to 85 °C 2
Maximum Three-State Leakage Current IOZ -0.25 0.25 µA VCC = 3.6 V, Vin = VIL or VIH, Vout = VCC or GND, TA = 25 °C 2
Maximum Three-State Leakage Current IOZ -2.5 2.5 µA VCC = 3.6 V, Vin = VIL or VIH, Vout = VCC or GND, TA = −40 to 85 °C 2
Quiescent Supply Current ICC 4 µA VCC = 3.6 V, Vin = VCC or GND, TA = 25 °C 2
Quiescent Supply Current ICC 40 µA VCC = 3.6 V, Vin = VCC or GND, TA = −40 to 85 °C 2
Propagation Delay Input to Output tPLH, tPHL 5.8 10.1 ns VCC = 2.7 V, CL = 15 pF, TA = 25 °C 3
Propagation Delay Input to Output tPLH, tPHL 1 13.5 ns VCC = 2.7 V, CL = 15 pF, TA = −40 to 85 °C 3
Propagation Delay Input to Output tPLH, tPHL 8.3 13.6 ns VCC = 2.7 V, CL = 50 pF, TA = 25 °C 3
Propagation Delay Input to Output tPLH, tPHL 1 17 ns VCC = 2.7 V, CL = 50 pF, TA = −40 to 85 °C 3
Propagation Delay Input to Output tPLH, tPHL 4.4 6.2 ns VCC = 3.3 ± 0.3 V, CL = 15 pF, TA = 25 °C 3
Propagation Delay Input to Output tPLH, tPHL 1 8.5 ns VCC = 3.3 ± 0.3 V, CL = 15 pF, TA = −40 to 85 °C 3
Propagation Delay Input to Output tPLH, tPHL 6.9 9.7 ns VCC = 3.3 ± 0.3 V, CL = 50 pF, TA = 25 °C 3
Propagation Delay Input to Output tPLH, tPHL 1 12 ns VCC = 3.3 ± 0.3 V, CL = 50 pF, TA = −40 to 85 °C 3
Output Enable Time OE to O tPZL, tPZH 5.3 9.3 ns VCC = 2.7 V, CL = 15 pF, RL = 1 kΩ, TA = 25 °C 3
Output Enable Time OE to O tPZL, tPZH 1 12.5 ns VCC = 2.7 V, CL = 15 pF, RL = 1 kΩ, TA = −40 to 85 °C 3
Output Enable Time OE to O tPZL, tPZH 7.8 12.8 ns VCC = 2.7 V, CL = 50 pF, RL = 1 kΩ, TA = 25 °C 3
Output Enable Time OE to O tPZL, tPZH 1 16 ns VCC = 2.7 V, CL = 50 pF, RL = 1 kΩ, TA = −40 to 85 °C 3
Output Enable Time OE to O tPZL, tPZH 4 5.6 ns VCC = 3.3 ± 0.3 V, CL = 15 pF, RL = 1 kΩ, TA = 25 °C 3
Output Enable Time OE to O tPZL, tPZH 1 7.5 ns VCC = 3.3 ± 0.3 V, CL = 15 pF, RL = 1 kΩ, TA = −40 to 85 °C 3
Output Enable Time OE to O tPZL, tPZH 6.5 9.1 ns VCC = 3.3 ± 0.3 V, CL = 50 pF, RL = 1 kΩ, TA = 25 °C 3
Output Enable Time OE to O tPZL, tPZH 1 11 ns VCC = 3.3 ± 0.3 V, CL = 50 pF, RL = 1 kΩ, TA = −40 to 85 °C 3
Output Disable Time OE to O tPLZ, tPHZ 10 15.7 ns VCC = 2.7 V, CL = 50 pF, RL = 1 kΩ, TA = 25 °C 3
Output Disable Time OE to O tPLZ, tPHZ 1 19 ns VCC = 2.7 V, CL = 50 pF, RL = 1 kΩ, TA = −40 to 85 °C 3
Output Disable Time OE to O tPLZ, tPHZ 8.3 11.2 ns VCC = 3.3 ± 0.3 V, CL = 50 pF, RL = 1 kΩ, TA = 25 °C 3
Output Disable Time OE to O tPLZ, tPHZ 1 13 ns VCC = 3.3 ± 0.3 V, CL = 50 pF, RL = 1 kΩ, TA = −40 to 85 °C 3

CAD (KiCad official)

  • Symbol: MC74LVX125DR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74lvx125dr2g-etched.step / mc74lvx125dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74lvx125dr2g.step / mc74lvx125dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 31a8383cd5f3bbbb, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF