component
MC74LCX74DTR2G
Public Made by Adomby adom
onsemi Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MC74LCX74DTR2G
onsemi · Flip Flops · TSSOP-14
MC74LCX74DTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CD1 | input | Direct clear input for flip-flop 1; a LOW level with SD1 HIGH asynchronously forces O1 LOW and O1 HIGH, and the device is rated for 5.0 V-tolerant inputs. |
| 2 | D1 | input | Data input for flip-flop 1, which must meet the setup and hold time requirements (ts 2.5 ns, th 1.5 ns at VCC = 3.3 V) relative to the CP1 clock. |
| 3 | CP1 | input | Clock pulse input for flip-flop 1; D1 is stored on the LOW-to-HIGH transition of CP1. |
| 4 | SD1 | input | Direct set input for flip-flop 1; a LOW level with CD1 HIGH asynchronously forces O1 HIGH and O1-bar LOW. |
| 5 | O1 | output | True output of flip-flop 1, rated for 24 mA balanced sink and source capability at VCC = 3.0 V to 3.6 V. |
| 6 | /O1 | output | Complementary (inverted) output of flip-flop 1, which is the logical inverse of O1. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | /O2 | output | Complementary (inverted) output of flip-flop 2, which is the logical inverse of O2. |
| 9 | O2 | output | True output of flip-flop 2, rated for 24 mA balanced sink and source capability at VCC = 3.0 V to 3.6 V. |
| 10 | SD2 | input | Direct set input for flip-flop 2; a LOW level with CD2 HIGH asynchronously forces O2 HIGH and O2-bar LOW. |
| 11 | CP2 | input | Clock pulse input for flip-flop 2; D2 is stored on the LOW-to-HIGH transition of CP2. |
| 12 | D2 | input | Data input for flip-flop 2, which must meet the setup and hold time requirements relative to the CP2 clock. |
| 13 | CD2 | input | Direct clear input for flip-flop 2; a LOW level with SD2 HIGH asynchronously forces O2 LOW and O2-bar HIGH. |
| 14 | VCC | power_in | Supply pin; the device is designed for 2.3 V to 3.6 V VCC operation (absolute maximum 7.0 V DC supply voltage). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (Operating) | VCC | 2 | 3.6 | V | Operating | 3 | |
| Supply Voltage (Data Retention Only) | VCC | 1.5 | 3.6 | V | Data retention only | 3 | |
| Input Voltage | VI | 0 | 5.5 | V | 3 | ||
| Output Voltage (HIGH or LOW State) | VO | 0 | V | HIGH or LOW State | 3 | ||
| HIGH Level Output Current | IOH | -24 | mA | VCC = 3.0 V − 3.6 V | 3 | ||
| HIGH Level Output Current | IOH | -12 | mA | VCC = 2.7 V − 3.0 V | 3 | ||
| HIGH Level Output Current | IOH | -8 | mA | VCC = 2.3 V − 2.7 V | 3 | ||
| LOW Level Output Current | IOL | 24 | mA | VCC = 3.0 V − 3.6 V | 3 | ||
| LOW Level Output Current | IOL | 12 | mA | VCC = 2.7 V − 3.0 V | 3 | ||
| LOW Level Output Current | IOL | 8 | mA | VCC = 2.3 V − 2.7 V | 3 | ||
| Operating Free-Air Temperature | TA | -40 | 85 | °C | 3 | ||
| Input Transition Rise or Fall Rate | t/V | 0 | 10 | ns/V | VIN from 0.8 V to 2.0 V, VCC = 3.0 V | 3 | |
| DC Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Voltage | VI | -0.5 | 7 | V | 3 | ||
| DC Output Voltage | VO | -0.5 | V | Output in HIGH or LOW State (Note 1) | 3 | ||
| DC Input Diode Current | IIK | -50 | mA | VI < GND | 3 | ||
| DC Output Diode Current | IOK | -50 | mA | VO < GND | 3 | ||
| DC Output Diode Current | IOK | 50 | mA | VO > VCC | 3 | ||
| DC Output Source/Sink Current | IO | 50 | mA | 3 | |||
| DC Supply Current Per Supply Pin | ICC | 100 | mA | 3 | |||
| DC Ground Current Per Ground Pin | IGND | 100 | mA | 3 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| HIGH Level Input Voltage | VIH | 1.7 | V | 2.3 V ≤ VCC ≤ 2.7 V | 4 | ||
| HIGH Level Input Voltage | VIH | 2 | V | 2.7 V ≤ VCC ≤ 3.6 V | 4 | ||
| LOW Level Input Voltage | VIL | 0.7 | V | 2.3 V ≤ VCC ≤ 2.7 V | 4 | ||
| LOW Level Input Voltage | VIL | 0.8 | V | 2.7 V ≤ VCC ≤ 3.6 V | 4 | ||
| HIGH Level Output Voltage | VOH | 1.8 | V | VCC = 2.3 V; IOH = −8 mA | 4 | ||
| HIGH Level Output Voltage | VOH | 2.2 | V | VCC = 2.7 V; IOH = −12 mA | 4 | ||
| HIGH Level Output Voltage | VOH | 2.4 | V | VCC = 3.0 V; IOH = −18 mA | 4 | ||
| LOW Level Output Voltage | VOL | 0.2 | V | 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 µA | 4 | ||
| LOW Level Output Voltage | VOL | 0.6 | V | VCC = 2.3 V; IOL = 8 mA | 4 | ||
| LOW Level Output Voltage | VOL | 0.4 | V | VCC = 2.7 V; IOL = 12 mA | 4 | ||
| LOW Level Output Voltage | VOL | 0.55 | V | VCC = 3.0 V; IOL = 24 mA | 4 | ||
| Power Off Leakage Current | IOFF | 10 | µA | VCC = 0, VIN = 5.5 V or VOUT = 5.5 V | 4 | ||
| Input Leakage Current | IIN | 5 | µA | VCC = 3.6 V, VIN = 5.5 V or GND | 4 | ||
| Quiescent Supply Current | ICC | 10 | µA | VCC = 3.6 V, VIN = 5.5 V or GND | 4 | ||
| Increase in ICC per Input | ICC | 500 | µA | 2.3 V ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V | 4 | ||
| Clock Pulse Frequency | fmax | 150 | MHz | VCC = 3.3 V ± 0.3 V, CL = 50 pF | 4 | ||
| Propagation Delay CPn to On or On | tPLH / tPHL | 1.5 | 7 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF; Waveform 1 | 4 | |
| Propagation Delay CPn to On or On | tPLH / tPHL | 1.5 | 8 | ns | VCC = 2.7 V, CL = 50 pF; Waveform 1 | 4 | |
| Propagation Delay CPn to On or On | tPLH / tPHL | 1.5 | 8.4 | ns | VCC = 2.5 V ± 0.2 V, CL = 30 pF; Waveform 1 | 4 | |
| Propagation Delay SDn or CDn to On or On | tPLH / tPHL | 1.5 | 7 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF; Waveform 2 | 4 | |
| Propagation Delay SDn or CDn to On or On | tPLH / tPHL | 1.5 | 8 | ns | VCC = 2.7 V, CL = 50 pF; Waveform 2 | 4 | |
| Propagation Delay SDn or CDn to On or On | tPLH / tPHL | 1.5 | 8.4 | ns | VCC = 2.5 V ± 0.2 V, CL = 30 pF; Waveform 2 | 4 | |
| Setup Time, HIGH or LOW Dn to CPn | ts | 2.5 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF; Waveform 1 | 4 | ||
| Setup Time, HIGH or LOW Dn to CPn | ts | 4 | ns | VCC = 2.5 V ± 0.2 V, CL = 30 pF; Waveform 1 | 4 | ||
| Hold Time, HIGH or LOW Dn to CPn | th | 1.5 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF; Waveform 1 | 4 | ||
| Hold Time, HIGH or LOW Dn to CPn | th | 2 | ns | VCC = 2.5 V ± 0.2 V, CL = 30 pF; Waveform 1 | 4 | ||
| Recovery Time SDn or CDn to CPn | trec | 2.5 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF; Waveform 3 | 4 | ||
| Recovery Time SDn or CDn to CPn | trec | 3 | ns | VCC = 2.7 V, CL = 50 pF; Waveform 3 | 4 | ||
| Recovery Time SDn or CDn to CPn | trec | 4.5 | ns | VCC = 2.5 V ± 0.2 V, CL = 30 pF; Waveform 3 | 4 | ||
| Output-to-Output Skew | tOSHL / tOSLH | 1 | ns | Note 3 | 4 |
CAD (KiCad official)
- Symbol:
MC74LCX74DTR2G - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
mc74lcx74dtr2g-etched.step/mc74lcx74dtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74lcx74dtr2g.step/mc74lcx74dtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
ae1fd5f931dc5a67, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).