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MC74LCX573DTR2G

Public Made by Adom

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onsemi Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74LCX573DTR2G

onsemi · Latches · TSSOP-20

MC74LCX573DTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output Enable input: when LOW the standard 3-state outputs are enabled, and when HIGH the outputs go to the high-impedance state without affecting data entering the latches.
2 D0 input Data input 0, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
3 D1 input Data input 1, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
4 D2 input Data input 2, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
5 D3 input Data input 3, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
6 D4 input Data input 4, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
7 D5 input Data input 5, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
8 D6 input Data input 6, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
9 D7 input Data input 7, which enters the latch when LE is HIGH; inputs are 5.0 V tolerant with VI up to 5.5 V and must not be left floating.
10 GND power_in Ground reference for the device.
11 LE input Latch Enable input: when HIGH the latches are transparent to Dn, and when LOW the latches store the data present a setup time before the HIGH-to-LOW transition of LE.
12 O7 tri_state 3-state latch output 7, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
13 O6 tri_state 3-state latch output 6, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
14 O5 tri_state 3-state latch output 5, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
15 O4 tri_state 3-state latch output 4, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
16 O3 tri_state 3-state latch output 3, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
17 O2 tri_state 3-state latch output 2, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
18 O1 tri_state 3-state latch output 1, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
19 O0 tri_state 3-state latch output 0, with balanced 24 mA sink and source capability at VCC of 3.0 V to 3.6 V.
20 VCC power_in Positive supply pin; the device is specified for 2.3 V to 3.6 V VCC operation with absolute maximum of 7.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 7 V 3
DC Input Voltage VI -0.5 7 V 3
DC Output Voltage VO -0.5 7 V Output in 3-State 3
DC Output Voltage VO -0.5 V Output in HIGH or LOW State (Note 1); -0.5 ≤ VO ≤ VCC + 0.5 3
DC Input Diode Current IIK -50 mA VI < GND 3
DC Output Diode Current IOK -50 mA VO < GND 3
DC Output Diode Current IOK 50 mA VO > VCC 3
DC Output Source/Sink Current IO -50 50 mA 3
DC Supply Current Per Supply Pin ICC -100 100 mA 3
DC Ground Current Per Ground Pin IGND -100 100 mA 3
Storage Temperature Range TSTG -65 150 °C 3
Supply Voltage Operating VCC 2 3.6 V Operating 3
Supply Voltage Data Retention Only VCC 1.5 3.6 V Data Retention Only 3
Input Voltage VI 0 5.5 V 3
HIGH Level Output Current IOH -24 mA VCC = 3.0 V − 3.6 V 3
HIGH Level Output Current IOH -12 mA VCC = 2.7 V − 3.0 V 3
HIGH Level Output Current IOH -8 mA VCC = 2.3 V − 2.7 V 3
LOW Level Output Current IOL 24 mA VCC = 3.0 V − 3.6 V 3
LOW Level Output Current IOL 12 mA VCC = 2.7 V − 3.0 V 3
LOW Level Output Current IOL 8 mA VCC = 2.3 V − 2.7 V 3
Operating Free-Air Temperature TA -55 125 °C 3
Input Transition Rise or Fall Rate t/V 0 10 ns/V VIN from 0.8 V to 2.0 V, VCC = 3.0 V 3
HIGH Level Input Voltage VIH 1.7 V 2.3 V ≤ VCC ≤ 2.7 V; TA = −55°C to +125°C 4
HIGH Level Input Voltage VIH 2 V 2.7 V ≤ VCC ≤ 3.6 V; TA = −55°C to +125°C 4
LOW Level Input Voltage VIL 0.7 V 2.3 V ≤ VCC ≤ 2.7 V; TA = −55°C to +125°C 4
LOW Level Input Voltage VIL 0.8 V 2.7 V ≤ VCC ≤ 3.6 V; TA = −55°C to +125°C 4
HIGH Level Output Voltage VOH 1.8 V VCC = 2.3 V; IOH = −8 mA; TA = −55°C to +125°C 4
HIGH Level Output Voltage VOH 2.2 V VCC = 2.7 V; IOH = −12 mA; TA = −55°C to +125°C 4
HIGH Level Output Voltage VOH 2.4 V VCC = 3.0 V; IOH = −18 mA; TA = −55°C to +125°C 4
LOW Level Output Voltage VOL 0.2 V 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 µA; TA = −55°C to +125°C 4
LOW Level Output Voltage VOL 0.6 V VCC = 2.3 V; IOL = 8 mA; TA = −55°C to +125°C 4
LOW Level Output Voltage VOL 0.4 V VCC = 2.7 V; IOL = 12 mA; TA = −55°C to +125°C 4
3-State Output Current IOZ -5 5 µA VCC = 3.6 V, VIN = VIH or VIL, VOUT = 0 to 5.5 V; TA = −55°C to +125°C 4
Input Leakage Current IIN -5 5 µA VCC = 3.6 V, VIN = 5.5 V or GND; TA = −55°C to +125°C 4
Quiescent Supply Current ICC 10 µA VCC = 3.6 V, VIN = 5.5 V or GND; TA = −55°C to +125°C 4
Increase in ICC per Input ICC 500 µA 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V; TA = −55°C to +125°C 4
Propagation Delay Dn to On tPLH, tPHL 1.5 8 ns VCC = 3.3 V ± 0.3 V; CL = 50 pF; TA = −55°C to +125°C 4
Propagation Delay Dn to On tPLH, tPHL 1.5 9 ns VCC = 2.7 V; CL = 50 pF; TA = −55°C to +125°C 4
Propagation Delay Dn to On tPLH, tPHL 1.5 9.6 ns VCC = 2.5 V ± 0.2 V; CL = 30 pF; TA = −55°C to +125°C 4
Propagation Delay LE to On tPLH, tPHL 1.5 8.5 ns VCC = 3.3 V ± 0.3 V; CL = 50 pF; TA = −55°C to +125°C 4
Propagation Delay LE to On tPLH, tPHL 1.5 9.5 ns VCC = 2.7 V; CL = 50 pF; TA = −55°C to +125°C 4
Propagation Delay LE to On tPLH, tPHL 1.5 10.5 ns VCC = 2.5 V ± 0.2 V; CL = 30 pF; TA = −55°C to +125°C 4
Output Enable Time to HIGH and LOW Level tPZH, tPZL 1.5 8.5 ns VCC = 3.3 V ± 0.3 V; CL = 50 pF; TA = −55°C to +125°C 4
Output Enable Time to HIGH and LOW Level tPZH, tPZL 1.5 9.5 ns VCC = 2.7 V; CL = 50 pF; TA = −55°C to +125°C 4
Output Enable Time to HIGH and LOW Level tPZH, tPZL 1.5 10.5 ns VCC = 2.5 V ± 0.2 V; CL = 30 pF; TA = −55°C to +125°C 4
Output Disable Time From High and Low Level tPHZ, tPLZ 1.5 6.5 ns VCC = 3.3 V ± 0.3 V; CL = 50 pF; TA = −55°C to +125°C 4
Output Disable Time From High and Low Level tPHZ, tPLZ 1.5 7 ns VCC = 2.7 V; CL = 50 pF; TA = −55°C to +125°C 4
Output Disable Time From High and Low Level tPHZ, tPLZ 1.5 7.8 ns VCC = 2.5 V ± 0.2 V; CL = 30 pF; TA = −55°C to +125°C 4
Setup Time, HIGH or LOW Dn to LE ts 2.5 ns VCC = 3.3 V ± 0.3 V; TA = −55°C to +125°C 4
Setup Time, HIGH or LOW Dn to LE ts 4 ns VCC = 2.5 V ± 0.2 V; TA = −55°C to +125°C 4
Hold Time, HIGH or LOW Dn to LE th 1.5 ns VCC = 3.3 V ± 0.3 V; TA = −55°C to +125°C 4
Hold Time, HIGH or LOW Dn to LE th 2 ns VCC = 2.5 V ± 0.2 V; TA = −55°C to +125°C 4
LE Pulse Width, HIGH tw 3.3 ns VCC = 3.3 V ± 0.3 V; TA = −55°C to +125°C 4
LE Pulse Width, HIGH tw 4 ns VCC = 2.5 V ± 0.2 V; TA = −55°C to +125°C 4

CAD (KiCad official)

  • Symbol: MC74LCX573DTR2G
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: mc74lcx573dtr2g-etched.step / mc74lcx573dtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74lcx573dtr2g.step / mc74lcx573dtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 55a038ba9229cc2c, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF