# MC74LCX541DTR2G

**onsemi** · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

MC74LCX541DTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable for O0 to O3 (OE1 HIGH forces the outputs to high impedance, per the truth table with OE2). |
| 2 | D0 | input | Data input 0; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 3 | D1 | input | Data input 1; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 4 | D2 | input | Data input 2; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 5 | D3 | input | Data input 3; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 6 | D4 | input | Data input 4; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 7 | D5 | input | Data input 5; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 8 | D6 | input | Data input 6; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 9 | D7 | input | Data input 7; 5 V tolerant, with VI rated up to 5.5 V in the recommended operating conditions. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | O7 | tri_state | 3-state non-inverting buffer output 7 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 12 | O6 | tri_state | 3-state non-inverting buffer output 6 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 13 | O5 | tri_state | 3-state non-inverting buffer output 5 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 14 | O4 | tri_state | 3-state non-inverting buffer output 4 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 15 | O3 | tri_state | 3-state non-inverting buffer output 3 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 16 | O2 | tri_state | 3-state non-inverting buffer output 2 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 17 | O1 | tri_state | 3-state non-inverting buffer output 1 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 18 | O0 | tri_state | 3-state non-inverting buffer output 0 with 24 mA balanced sink and source capability; high impedance when disabled. |
| 19 | OE2 | input | Active-low output enable for O4 to O7 (OE2 HIGH forces the outputs to high impedance, per the truth table with OE1). |
| 20 | VCC | power_in | Positive supply; 2.0 V to 3.6 V operating per the recommended operating conditions (absolute maximum 7.0 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage, operating | VCC | 2 | 3.3 | 3.6 | V | Operating | 3 |
| DC Supply Voltage, data retention only | VCC | 1.5 | 3.3 | 3.6 | V | Data Retention Only | 3 |
| DC Input Voltage | VI | 0 |  | 5.5 | V |  | 3 |
| Output Voltage, HIGH or LOW state | VO | 0 |  |  | V | HIGH or LOW state; printed maximum is VCC | 3 |
| Output Voltage, 3-state | VO | 0 |  | 5.5 | V | 3-state | 3 |
| HIGH Level Output Current | IOH |  |  | -24 | mA | VCC = 3.0 V to 3.6 V | 3 |
| LOW Level Output Current | IOL |  |  | 24 | mA | VCC = 3.0 V to 3.6 V | 3 |
| HIGH Level Output Current | IOH |  |  | -12 | mA | VCC = 2.7 V to 3.0 V | 3 |
| LOW Level Output Current | IOL |  |  | 12 | mA | VCC = 2.7 V to 3.0 V | 3 |
| Operating Free-Air Temperature | TA | -40 |  | 85 | °C |  | 3 |
| Input Transition Rise or Fall Rate | t/V | 0 |  | 10 | ns/V | VIN from 0.8 V to 2.0 V, VCC = 3.0 V | 3 |
| HIGH Level Input Voltage | VIH | 2 |  |  | V | 2.7 V ≤ VCC ≤ 3.6 V; TA = −40°C to +85°C | 3 |
| LOW Level Input Voltage | VIL |  |  | 0.8 | V | 2.7 V ≤ VCC ≤ 3.6 V; TA = −40°C to +85°C | 3 |
| HIGH Level Output Voltage | VOH | 2.2 |  |  | V | VCC = 2.7 V; IOH = −12 mA | 3 |
| HIGH Level Output Voltage | VOH | 2.4 |  |  | V | VCC = 3.0 V; IOH = −18 mA | 3 |
| LOW Level Output Voltage | VOL |  |  | 0.2 | V | 2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 µA | 3 |
| LOW Level Output Voltage | VOL |  |  | 0.4 | V | VCC = 2.7 V; IOL = 12 mA | 3 |
| LOW Level Output Voltage | VOL |  |  | 0.55 | V | VCC = 3.0 V; IOL = 24 mA | 3 |
| 3-State Output Current | IOZ | -5 |  | 5 | µA | VCC = 3.6 V, VIN = VIH or VIL, VOUT = 0 to 5.5 V | 3 |
| Power Off Leakage Current | IOFF |  |  | 10 | µA | VCC = 0, VIN = 5.5 V or VOUT = 5.5 V | 3 |
| Input Leakage Current | IIN | -5 |  | 5 | µA | VCC = 3.6 V, VIN = 5.5 V or GND | 3 |
| Quiescent Supply Current | ICC |  |  | 10 | µA | VCC = 3.6 V, VIN = 5.5 V or GND | 3 |
| Increase in ICC per Input | ICC |  |  | 500 | µA | 2.3 V ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V | 3 |
| Propagation Delay Input to Output, tPLH | tPLH | 1.5 |  | 6.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Propagation Delay Input to Output, tPHL | tPHL | 1.5 |  | 6.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Propagation Delay Input to Output, tPLH | tPLH |  |  | 7.5 | ns | VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Propagation Delay Input to Output, tPHL | tPHL |  |  | 7.5 | ns | VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Enable Time to HIGH Level, tPZH | tPZH | 1.5 |  | 8.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Enable Time to LOW Level, tPZL | tPZL | 1.5 |  | 8.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Enable Time to HIGH Level, tPZH | tPZH |  |  | 9.5 | ns | VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Enable Time to LOW Level, tPZL | tPZL |  |  | 9.5 | ns | VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Disable Time From HIGH Level, tPHZ | tPHZ | 1.5 |  | 7.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Disable Time From LOW Level, tPLZ | tPLZ | 1.5 |  | 7.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Disable Time From HIGH Level, tPHZ | tPHZ |  |  | 8.5 | ns | VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output Disable Time From LOW Level, tPLZ | tPLZ |  |  | 8.5 | ns | VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns; TA = −40°C to +85°C | 4 |
| Output-to-Output Skew, HIGH-to-LOW | tOSHL |  |  | 1 | ns | Note 3; same-direction switching; column VCC not explicit in table | 4 |
| Output-to-Output Skew, LOW-to-HIGH | tOSLH |  |  | 1 | ns | Note 3; same-direction switching; column VCC not explicit in table | 4 |
| Dynamic LOW Peak Voltage | VOLP |  |  | 0.8 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25°C | 4 |
| Dynamic LOW Valley Voltage | VOLV |  |  | 0.8 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25°C | 4 |
| DC Supply Voltage | VCC | -0.5 |  | 7 | V |  | 2 |
| DC Input Voltage | VI | -0.5 |  | 7 | V | −0.5 ≤ VI ≤ +7.0 | 2 |
| DC Output Voltage, 3-state | VO | -0.5 |  | 7 | V | Output in 3-state | 2 |
| DC Output Voltage, HIGH or LOW state | VO | -0.5 |  |  | V | Output in HIGH or LOW state (Note 1); printed maximum is VCC + 0.5 | 2 |
| DC Input Diode Current | IIK |  |  | -50 | mA | VI < GND | 2 |
| DC Output Diode Current, VO < GND | IOK |  |  | -50 | mA | VO < GND | 2 |
| DC Output Diode Current, VO > VCC | IOK |  |  | 50 | mA | VO > VCC | 2 |
| DC Output Source/Sink Current | IO | -50 |  | 50 | mA |  | 2 |
| DC Supply Current per Supply Pin | ICC | -100 |  | 100 | mA | Per supply pin | 2 |
| DC Ground Current per Ground Pin | IGND | -100 |  | 100 | mA | Per ground pin | 2 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 2 |

## CAD (KiCad official)

- Symbol: `MC74LCX541DTR2G`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `mc74lcx541dtr2g-etched.step` / `mc74lcx541dtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74lcx541dtr2g.step` / `mc74lcx541dtr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74lcx541dtr2-d.pdf) (8 pp, sha256 `755fdc269a6069d7`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mc74lcx541dtr2g-datasheet.pdf)