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MC74LCX374DTR2G

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onsemi Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74LCX374DTR2G

onsemi · Flip Flops · TSSOP-20

MC74LCX374DTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-LOW output enable: when LOW the eight outputs show the stored register contents, and when HIGH the outputs go to high impedance without affecting the flip-flops.
2 O0 tri_state 3-state true output of flip-flop 0, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
3 D0 input Data input to flip-flop 0, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
4 D1 input Data input to flip-flop 1, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
5 O1 tri_state 3-state true output of flip-flop 1, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
6 O2 tri_state 3-state true output of flip-flop 2, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
7 D2 input Data input to flip-flop 2, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
8 D3 input Data input to flip-flop 3, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
9 O3 tri_state 3-state true output of flip-flop 3, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
10 GND power_in Device ground, the reference for all voltages specified in the datasheet.
11 CP input Clock input: the flip-flops store their D inputs on the LOW-to-HIGH transition, with maximum clock frequency 150 MHz and minimum pulse width 3.3 ns.
12 O4 tri_state 3-state true output of flip-flop 4, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
13 D4 input Data input to flip-flop 4, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
14 D5 input Data input to flip-flop 5, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
15 O5 tri_state 3-state true output of flip-flop 5, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
16 O6 tri_state 3-state true output of flip-flop 6, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
17 D6 input Data input to flip-flop 6, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
18 D7 input Data input to flip-flop 7, captured on the LOW-to-HIGH CP transition, with input voltage rated up to 5.5 V and setup/hold times of 2.5 ns / 1.5 ns.
19 O7 tri_state 3-state true output of flip-flop 7, rated for 24 mA balanced sink and source drive at VCC = 3.0 V to 3.6 V.
20 VCC power_in Positive supply, specified for 2.0 V to 3.6 V operation (1.5 V minimum for data retention only).

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage, Operating VCC 2 3.3 3.6 V Operating 3
DC Supply Voltage, Data Retention Only VCC 1.5 3.3 3.6 V Data retention only 3
Input Voltage VI 0 5.5 V 3
Output Voltage (HIGH or LOW State) VO 0 V HIGH or LOW state; upper limit printed as VCC 3
Output Voltage (3-State) VO 0 5.5 V 3-state 3
HIGH Level Output Current IOH -24 mA VCC = 3.0 V to 3.6 V 3
LOW Level Output Current IOL 24 mA VCC = 3.0 V to 3.6 V 3
HIGH Level Output Current IOH -12 mA VCC = 2.7 V to 3.0 V 3
LOW Level Output Current IOL 12 mA VCC = 2.7 V to 3.0 V 3
Operating Free-Air Temperature TA -40 85 °C 3
Input Transition Rise or Fall Rate Δt/ΔV 0 10 ns/V VIN from 0.8 V to 2.0 V, VCC = 3.0 V 3
DC Supply Voltage VCC -0.5 7 V 3
DC Input Voltage VI -0.5 7 V 3
DC Output Voltage VO -0.5 7 V Output in 3-state 3
DC Output Voltage VO -0.5 V Output in HIGH or LOW state; upper limit printed as VCC + 0.5 (Note 1) 3
DC Input Diode Current IIK -50 mA VI < GND 3
DC Output Diode Current IOK -50 mA VO < GND 3
DC Output Diode Current IOK 50 mA VO > VCC 3
DC Output Source/Sink Current IO -50 50 mA 3
DC Supply Current ICC -100 100 mA Per supply pin 3
DC Ground Current IGND -100 100 mA Per ground pin 3
Storage Temperature Range TSTG -65 150 °C 3
HIGH Level Input Voltage VIH 2 V 2.7 V ≤ VCC ≤ 3.6 V; TA = −40°C to +85°C 4
LOW Level Input Voltage VIL 0.8 V 2.7 V ≤ VCC ≤ 3.6 V; TA = −40°C to +85°C 4
HIGH Level Output Voltage VOH 2.2 V VCC = 2.7 V; IOH = −12 mA 4
HIGH Level Output Voltage VOH 2.4 V VCC = 3.0 V; IOH = −18 mA 4
LOW Level Output Voltage VOL 0.2 V 2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 µA 4
LOW Level Output Voltage VOL 0.4 V VCC = 2.7 V; IOL = 12 mA 4
LOW Level Output Voltage VOL 0.55 V VCC = 3.0 V; IOL = 24 mA 4
3-State Output Current IOZ -5 5 µA VCC = 3.6 V, VIN = VIH or VIL, VOUT = 0 to 5.5 V 4
Power Off Leakage Current IOFF 10 µA VCC = 0, VIN = 5.5 V or VOUT = 5.5 V 4
Input Leakage Current IIN -5 5 µA VCC = 3.6 V, VIN = 5.5 V or GND 4
Quiescent Supply Current ICC 10 µA VCC = 3.6 V, VIN = 5.5 V or GND 4
Increase in ICC per Input ΔICC 500 µA 2.3 V ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 4
Clock Pulse Frequency fmax 150 MHz Waveform 1; tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω; VCC = 3.0 V to 3.6 V 4
Propagation Delay CP to On tPLH, tPHL 1.5 8.5 ns Waveform 1; VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω 4
Propagation Delay CP to On tPLH, tPHL 1.5 9.5 ns Waveform 1; VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 4
Output Enable Time to HIGH and LOW Levels tPZH, tPZL 1.5 8.5 ns Waveform 2; VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω 4
Output Enable Time to HIGH and LOW Levels tPZH, tPZL 1.5 9.5 ns Waveform 2; VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 4
Output Disable Time from HIGH and LOW Levels tPHZ, tPLZ 1.5 7.5 ns Waveform 2; VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω 4
Output Disable Time from HIGH and LOW Levels tPHZ, tPLZ 1.5 8.5 ns Waveform 2; VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 4
Setup Time, HIGH or LOW Dn to CP ts 2.5 ns Waveform 1; VCC = 3.0 V to 3.6 V and 2.7 V; CL = 50 pF; RL = 500 Ω 4
Hold Time, HIGH or LOW Dn to CP th 1.5 ns Waveform 1; VCC = 3.0 V to 3.6 V and 2.7 V; CL = 50 pF; RL = 500 Ω 4
CP Pulse Width, HIGH or LOW tw 3.3 ns Waveform 3; VCC = 3.0 V to 3.6 V and 2.7 V; CL = 50 pF; RL = 500 Ω 4
Output-to-Output Skew (tOSHL) tOSHL 1 ns Any outputs switching HIGH-to-LOW; VCC = 3.0 V to 3.6 V and 2.7 V; parameter guaranteed by design 4
Output-to-Output Skew (tOSLH) tOSLH 1 ns Any outputs switching LOW-to-HIGH; VCC = 3.0 V to 3.6 V and 2.7 V; parameter guaranteed by design 4
Dynamic LOW Peak Voltage VOLP 0.8 V TA = +25°C; VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 5
Dynamic LOW Valley Voltage VOLV 0.8 V TA = +25°C; VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 5

CAD (KiCad official)

  • Symbol: MC74LCX374DTR2G
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: mc74lcx374dtr2g-etched.step / mc74lcx374dtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74lcx374dtr2g.step / mc74lcx374dtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 2f286f9ef81c5eb1, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF