component
MC74LCX14DR2G
Public Made by Adomby adom
onsemi Inverters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74LCX14DR2G
onsemi · Inverters · SOIC-14
MC74LCX14DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Data input of inverter gate 1; the Schmitt-trigger input accepts up to 5.5 V (VI maximum 5.5 V), so it can be driven from 5.0 V devices. |
| 2 | Y1 | output | Inverted output of gate 1 with 24 mA balanced source/sink capability at VCC 3.0 V to 3.6 V (IOH −24 mA, IOL +24 mA). |
| 3 | A2 | input | Data input of inverter gate 2; the Schmitt-trigger input accepts up to 5.5 V (VI maximum 5.5 V), so it can be driven from 5.0 V devices. |
| 4 | Y2 | output | Inverted output of gate 2 with 24 mA balanced source/sink capability at VCC 3.0 V to 3.6 V (IOH −24 mA, IOL +24 mA). |
| 5 | A3 | input | Data input of inverter gate 3; the Schmitt-trigger input accepts up to 5.5 V (VI maximum 5.5 V), so it can be driven from 5.0 V devices. |
| 6 | Y3 | output | Inverted output of gate 3 with 24 mA balanced source/sink capability at VCC 3.0 V to 3.6 V (IOH −24 mA, IOL +24 mA). |
| 7 | GND | power_in | Ground reference pin for the device; the datasheet specifies inputs and outputs relative to GND (VI and VO minimum 0 V). |
| 8 | Y4 | output | Inverted output of gate 4 with 24 mA balanced source/sink capability at VCC 3.0 V to 3.6 V (IOH −24 mA, IOL +24 mA). |
| 9 | A4 | input | Data input of inverter gate 4; the Schmitt-trigger input accepts up to 5.5 V (VI maximum 5.5 V), so it can be driven from 5.0 V devices. |
| 10 | Y5 | output | Inverted output of gate 5 with 24 mA balanced source/sink capability at VCC 3.0 V to 3.6 V (IOH −24 mA, IOL +24 mA). |
| 11 | A5 | input | Data input of inverter gate 5; the Schmitt-trigger input accepts up to 5.5 V (VI maximum 5.5 V), so it can be driven from 5.0 V devices. |
| 12 | Y6 | output | Inverted output of gate 6 with 24 mA balanced source/sink capability at VCC 3.0 V to 3.6 V (IOH −24 mA, IOL +24 mA). |
| 13 | A6 | input | Data input of inverter gate 6; the Schmitt-trigger input accepts up to 5.5 V (VI maximum 5.5 V), so it can be driven from 5.0 V devices. |
| 14 | VCC | power_in | Positive supply pin; the device is designed for 2.3 V to 3.6 V VCC operation (1.5 V minimum for data retention only). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (Operating) | VCC | 2 | 3.6 | V | Operating; typ printed as 2.5 to 3.3 | 3 | |
| Supply Voltage (Data Retention Only) | VCC | 1.5 | 3.6 | V | Data retention only | 3 | |
| Input Voltage | VI | 0 | 5.5 | V | 3 | ||
| Output Voltage (HIGH or LOW State) | VO | 0 | V | HIGH or LOW state; upper limit printed as VCC | 3 | ||
| HIGH Level Output Current | IOH | -24 | mA | VCC = 3.0 V to 3.6 V | 3 | ||
| HIGH Level Output Current | IOH | -12 | mA | VCC = 2.7 V to 3.0 V | 3 | ||
| HIGH Level Output Current | IOH | -8 | mA | VCC = 2.3 V to 2.7 V | 3 | ||
| LOW Level Output Current | IOL | 24 | mA | VCC = 3.0 V to 3.6 V | 3 | ||
| LOW Level Output Current | IOL | 12 | mA | VCC = 2.7 V to 3.0 V | 3 | ||
| LOW Level Output Current | IOL | 8 | mA | VCC = 2.3 V to 2.7 V | 3 | ||
| Operating Free-Air Temperature | TA | -40 | 85 | °C | 3 | ||
| DC Supply Voltage | VCC | -0.5 | 7 | V | 2 | ||
| DC Input Voltage | VI | -0.5 | 7 | V | 2 | ||
| DC Output Voltage | VO | -0.5 | V | Output in HIGH or LOW state (Note 1); upper limit printed as VCC + 0.5 | 2 | ||
| DC Input Diode Current | IIK | -50 | mA | VI < GND | 2 | ||
| DC Output Diode Current | IOK | -50 | mA | VO < GND | 2 | ||
| DC Output Diode Current | IOK | 50 | mA | VO > VCC | 2 | ||
| DC Output Source/Sink Current | IO | 50 | mA | 2 | |||
| DC Supply Current | ICC | 100 | mA | Per supply pin | 2 | ||
| DC Ground Current | IGND | 100 | mA | Per ground pin | 2 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Positive Input Threshold Voltage | VT+ | 0.9 | 1.7 | V | VCC = 2.5 V; TA = -40 to 85 °C (Figure 3) | 3 | |
| Positive Input Threshold Voltage | VT+ | 1.2 | 2.2 | V | VCC = 3.0 V; TA = -40 to 85 °C (Figure 3) | 3 | |
| Negative Input Threshold Voltage | VT- | 0.4 | 1.1 | V | VCC = 2.5 V; TA = -40 to 85 °C (Figure 3) | 3 | |
| Negative Input Threshold Voltage | VT- | 0.6 | 1.5 | V | VCC = 3.0 V; TA = -40 to 85 °C (Figure 3) | 3 | |
| Input Hysteresis Voltage | VH | 0.3 | 1 | V | VCC = 2.5 V; TA = -40 to 85 °C (Figure 3) | 3 | |
| Input Hysteresis Voltage | VH | 0.4 | 1.2 | V | VCC = 3.0 V; TA = -40 to 85 °C (Figure 3) | 3 | |
| HIGH Level Output Voltage | VOH | 1.8 | V | VCC = 2.3 V; IOH = -8 mA; TA = -40 to 85 °C | 3 | ||
| HIGH Level Output Voltage | VOH | 2.2 | V | VCC = 2.7 V; IOH = -12 mA; TA = -40 to 85 °C | 3 | ||
| HIGH Level Output Voltage | VOH | 2.4 | V | VCC = 3.0 V; IOH = -18 mA; TA = -40 to 85 °C | 3 | ||
| LOW Level Output Voltage | VOL | 0.2 | V | 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 µA; TA = -40 to 85 °C | 3 | ||
| LOW Level Output Voltage | VOL | 0.3 | V | VCC = 2.3 V; IOL = 8 mA; TA = -40 to 85 °C | 3 | ||
| LOW Level Output Voltage | VOL | 0.4 | V | VCC = 2.7 V; IOL = 12 mA; TA = -40 to 85 °C | 3 | ||
| LOW Level Output Voltage | VOL | 0.55 | V | VCC = 3.0 V; IOL = 24 mA; TA = -40 to 85 °C | 3 | ||
| Power Off Leakage Current | IOFF | 10 | µA | VCC = 0, VIN = 5.5 V or VOUT = 5.5 V; TA = -40 to 85 °C | 3 | ||
| Input Leakage Current | IIN | 5 | µA | VCC = 3.6 V, VIN = 5.5 V or GND; TA = -40 to 85 °C | 3 | ||
| Quiescent Supply Current | ICC | 10 | µA | VCC = 3.6 V, VIN = 5.5 V or GND; TA = -40 to 85 °C | 3 | ||
| Increase in ICC per Input | ICC | 500 | µA | 2.3 V ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V; TA = -40 to 85 °C | 3 | ||
| Propagation Delay Input to Output (tPLH) | tPLH | 1.5 | 6.5 | ns | VCC = 3.3 V ± 0.3 V; CL = 50 pF; TA = -40 to +85 °C | 4 | |
| Propagation Delay Input to Output (tPHL) | tPHL | 1.5 | 6.5 | ns | VCC = 3.3 V ± 0.3 V; CL = 50 pF; TA = -40 to +85 °C | 4 | |
| Propagation Delay Input to Output (tPLH) | tPLH | 1.5 | 7.5 | ns | VCC = 2.7 V; CL = 50 pF; TA = -40 to +85 °C | 4 | |
| Propagation Delay Input to Output (tPHL) | tPHL | 1.5 | 7.5 | ns | VCC = 2.7 V; CL = 50 pF; TA = -40 to +85 °C | 4 | |
| Propagation Delay Input to Output (tPLH) | tPLH | 1.5 | 7.8 | ns | VCC = 2.5 V ± 0.2 V; CL = 30 pF; TA = -40 to +85 °C | 4 | |
| Propagation Delay Input to Output (tPHL) | tPHL | 1.5 | 7.8 | ns | VCC = 2.5 V ± 0.2 V; CL = 30 pF; TA = -40 to +85 °C | 4 | |
| Output-to-Output Skew (HIGH-to-LOW) | tOSHL | 1 | ns | Note 2 | 4 | ||
| Output-to-Output Skew (LOW-to-HIGH) | tOSLH | 1 | ns | Note 2 | 4 | ||
| Dynamic LOW Peak Voltage | VOLP | 0.8 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25 °C | 4 | ||
| Dynamic LOW Peak Voltage | VOLP | 0.6 | V | VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V; TA = +25 °C | 4 | ||
| Dynamic LOW Valley Voltage | VOLV | -0.8 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25 °C | 4 | ||
| Dynamic LOW Valley Voltage | VOLV | -0.6 | V | VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V; TA = +25 °C | 4 |
CAD (KiCad official)
- Symbol:
MC74LCX14DR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74lcx14dr2g-etched.step/mc74lcx14dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74lcx14dr2g.step/mc74lcx14dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
0828d0b9f4b06b97, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).