component
MC74LCX07DTR2G
Public Made by Adomby adom
onsemi Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 13d ago |
| viewers | 13d ago |
| mc74lcx07dtr2g-etched.glb | 13d ago |
| mc74lcx07dtr2g-etched.step | 13d ago |
| mc74lcx07dtr2g-hero.glb | 13d ago |
| mc74lcx07dtr2g-hero.overlay.json | 13d ago |
| mc74lcx07dtr2g.glb | 13d ago |
| mc74lcx07dtr2g.kicad_mod | 13d ago |
| mc74lcx07dtr2g.kicad_sym | 13d ago |
| mc74lcx07dtr2g.lbr | 13d ago |
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| package.json | 13d ago |
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| README.md | 13d ago |
MC74LCX07DTR2G
onsemi · Logic ICs · TSSOP-14
MC74LCX07DTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Data input A0 is a high-impedance TTL compatible input that is 5.5 V tolerant. |
| 2 | O0 | output | Open drain output O0 has 24 mA sink capability and is 5.0 V tolerant. |
| 3 | A1 | input | Data input A1 is a high-impedance TTL compatible input that is 5.5 V tolerant. |
| 4 | O1 | output | Open drain output O1 has 24 mA sink capability and is 5.0 V tolerant. |
| 5 | A2 | input | Data input A2 is a high-impedance TTL compatible input that is 5.5 V tolerant. |
| 6 | O2 | output | Open drain output O2 has 24 mA sink capability and is 5.0 V tolerant. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | O5 | output | Open drain output O5 has 24 mA sink capability and is 5.0 V tolerant. |
| 9 | A5 | input | Data input A5 is a high-impedance TTL compatible input that is 5.5 V tolerant. |
| 10 | O4 | output | Open drain output O4 has 24 mA sink capability and is 5.0 V tolerant. |
| 11 | A4 | input | Data input A4 is a high-impedance TTL compatible input that is 5.5 V tolerant. |
| 12 | O3 | output | Open drain output O3 has 24 mA sink capability and is 5.0 V tolerant. |
| 13 | A3 | input | Data input A3 is a high-impedance TTL compatible input that is 5.5 V tolerant. |
| 14 | VCC | power_in | Positive supply pin, designed for 2.3 to 3.6 V VCC operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | 2 | ||
| DC Input Voltage | VI | -0.5 | 7 | V | 2 | ||
| DC Output Voltage | VO | -0.5 | 7 | V | Output in HIGH or LOW State (Note 1) | 2 | |
| DC Input Diode Current | IIK | -50 | mA | VI < GND | 2 | ||
| DC Output Diode Current | IOK | -50 | mA | VO < GND | 2 | ||
| DC Output Diode Current | IOK | 50 | mA | VO > VCC | 2 | ||
| DC Output/Sink Current | IO | 50 | mA | 2 | |||
| DC Supply Current Per Supply Pin | ICC | 100 | mA | 2 | |||
| DC Ground Current Per Ground Pin | IGND | 100 | mA | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | C | 2 | ||
| Supply Voltage Operating | VCC | 2 | 5.5 | V | Operating | 3 | |
| Supply Voltage Data Retention Only | VCC | 1.5 | 5.5 | V | Data Retention Only | 3 | |
| Input Voltage | VI | 0 | 5.5 | V | 3 | ||
| Output Voltage (HIGH or LOW State) | VO | 0 | 5.5 | V | 3 | ||
| HIGH Level Output Current | IOH | -24 | mA | VCC = 3.0 V-3.6 V | 3 | ||
| HIGH Level Output Current | IOH | -12 | mA | VCC = 2.7 V-3.0 V | 3 | ||
| HIGH Level Output Current | IOH | -8 | mA | VCC = 2.3 V-2.7 V | 3 | ||
| LOW Level Output Current | IOL | 24 | mA | VCC = 3.0 V-3.6 V | 3 | ||
| LOW Level Output Current | IOL | 12 | mA | VCC = 2.7 V-3.0 V | 3 | ||
| LOW Level Output Current | IOL | 8 | mA | VCC = 2.3 V-2.7 V | 3 | ||
| Operating Free-Air Temperature | TA | -40 | 85 | C | 3 | ||
| Input Transition Rise or Fall Rate | t/V | 0 | 10 | ns/V | VIN from 0.8 V to 2.0 V, VCC = 3.0 V | 3 | |
| HIGH Level Input Voltage | VIH | 1.7 | V | 2.3 V ≤ VCC ≤ 2.7 V; TA = −40C to +85C | 3 | ||
| HIGH Level Input Voltage | VIH | 2 | V | 2.7 V ≤ VCC ≤ 3.6 V; TA = −40C to +85C | 3 | ||
| HIGH Level Input Voltage | VIH | 3.125 | V | 4.5 V ≤ VCC ≤ 5.25 V; TA = −40C to +85C | 3 | ||
| LOW Level Input Voltage | VIL | 0.7 | V | 2.3 V ≤ VCC ≤ 2.7 V; TA = −40C to +85C | 3 | ||
| LOW Level Input Voltage | VIL | 0.8 | V | 2.7 V ≤ VCC ≤ 3.6 V; TA = −40C to +85C | 3 | ||
| LOW Level Output Voltage | VOL | 0.2 | V | 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 µA; TA = −40C to +85C | 3 | ||
| LOW Level Output Voltage | VOL | 0.3 | V | VCC = 2.3 V; IOL = 8 mA; TA = −40C to +85C | 3 | ||
| LOW Level Output Voltage | VOL | 0.4 | V | VCC = 2.7 V; IOL = 12 mA; TA = −40C to +85C | 3 | ||
| LOW Level Output Voltage | VOL | 0.55 | V | VCC = 3.0 V; IOL = 24 mA; TA = −40C to +85C | 3 | ||
| 3-State Output Current | IOZ | 5 | µA | VCC = 3.6 V, VIN = VIH or VIL, VOUT = 0 to 5.5 V; TA = −40C to +85C | 3 | ||
| Power Off Leakage Current | IOFF | 10 | µA | VCC = 0, VIN = 5.5 V or VOUT = 5.5 V; TA = −40C to +85C | 3 | ||
| Input Leakage Current | IIN | 5 | µA | VCC = 3.6 V, VIN = 5.5 V or GND; TA = −40C to +85C | 3 | ||
| Quiescent Supply Current | ICC | 10 | µA | VCC = 3.6 V, VIN = 5.5 V or GND; TA = −40C to +85C | 3 | ||
| Increase in ICC per Input | ICC | 500 | µA | 2.3 V ≤ VCC ≤ 3.6 V; TA = −40C to +85C | 3 | ||
| Increase in ICC per Input | ICC | 1 | mA | 4.5 V ≤ VCC ≤ 5.5 V; VCC = 5.25 V, one input at 3.125 V, other inputs at VCC or GND; TA = −40C to +85C | 3 | ||
| Propagation Delay Input to Output tPLZ | tPLZ | 0.5 | 3 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = −40C to +85C | 3 | |
| Propagation Delay Input to Output tPZL | tPZL | 0.5 | 3 | ns | VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = −40C to +85C | 3 | |
| Propagation Delay Input to Output tPLZ | tPLZ | 0.8 | 3.7 | ns | VCC = 2.7 V, CL = 50 pF; TA = −40C to +85C | 3 | |
| Propagation Delay Input to Output tPZL | tPZL | 0.8 | 3.7 | ns | VCC = 2.7 V, CL = 50 pF; TA = −40C to +85C | 3 | |
| Propagation Delay Input to Output tPLZ | tPLZ | 0.8 | 3.8 | ns | VCC = 2.5 V ± 0.2 V, CL = 30 pF; TA = −40C to +85C | 3 | |
| Propagation Delay Input to Output tPZL | tPZL | 0.8 | 3.8 | ns | VCC = 2.5 V ± 0.2 V, CL = 30 pF; TA = −40C to +85C | 3 | |
| Dynamic LOW Peak Voltage | VOLP | 0.9 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25C | 4 | ||
| Dynamic LOW Peak Voltage | VOLP | 0.7 | V | VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V; TA = +25C | 4 | ||
| Dynamic LOW Valley Voltage | VOLV | -0.8 | V | VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25C | 4 | ||
| Dynamic LOW Valley Voltage | VOLV | -0.6 | V | VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V; TA = +25C | 4 | ||
| Input Capacitance | CIN | 7 | pF | VCC = 3.3 V, VI = 0 V or VCC | 4 | ||
| Output Capacitance | COUT | 8 | pF | VCC = 3.3 V, VI = 0 V or VCC | 4 | ||
| Power Dissipation Capacitance | CPD | 25 | pF | 10 MHz, VCC = 3.3 V, VI = 0 V or VCC | 4 |
CAD (KiCad official)
- Symbol:
MC74LCX07DTR2G - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
mc74lcx07dtr2g-etched.step/mc74lcx07dtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74lcx07dtr2g.step/mc74lcx07dtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
97ec102b3a6a963d, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).