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MC74LCX00DTR2G

Public Made by Adom

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onsemi Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MC74LCX00DTR2G

onsemi · Logic Gates · TSSOP-14

MC74LCX00DTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Data input A of NAND gate 0; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
2 B0 input Data input B of NAND gate 0; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
3 O0 output Output of NAND gate 0, rated for 24 mA balanced sink and source at VCC 3.0 V to 3.6 V (IOL +24 mA, IOH −24 mA).
4 A1 input Data input A of NAND gate 1; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
5 B1 input Data input B of NAND gate 1; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
6 O1 output Output of NAND gate 1, rated for 24 mA balanced sink and source at VCC 3.0 V to 3.6 V (IOL +24 mA, IOH −24 mA).
7 GND power_in Ground reference; the datasheet limits ground current to 100 mA per ground pin (absolute maximum).
8 O3 output Output of NAND gate 3, rated for 24 mA balanced sink and source at VCC 3.0 V to 3.6 V (IOL +24 mA, IOH −24 mA).
9 B3 input Data input B of NAND gate 3; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
10 A3 input Data input A of NAND gate 3; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
11 O2 output Output of NAND gate 2, rated for 24 mA balanced sink and source at VCC 3.0 V to 3.6 V (IOL +24 mA, IOH −24 mA).
12 B2 input Data input B of NAND gate 2; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
13 A2 input Data input A of NAND gate 2; it is 5 V tolerant with VI specified up to 5.5 V and must not be left floating.
14 VCC power_in Positive supply; recommended operating range is 2.0 V to 3.6 V (1.5 V for data retention only) and the absolute maximum DC supply is 7.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Operating VCC 2 3.6 V Operating; typ cell prints '2.5, 3.3' (not a single value) 3
DC Supply Voltage Data Retention Only VCC 1.5 3.6 V Data retention only 3
Input Voltage VI 0 5.5 V 3
Output Voltage (HIGH or LOW State, 3-State) VO 0 V Max printed as VCC 3
HIGH Level Output Current IOH -24 mA VCC = 3.0 V to 3.6 V 3
HIGH Level Output Current IOH -12 mA VCC = 2.7 V to 3.0 V 3
HIGH Level Output Current IOH -8 mA VCC = 2.3 V to 2.7 V 3
LOW Level Output Current IOL 24 mA VCC = 3.0 V to 3.6 V 3
LOW Level Output Current IOL 12 mA VCC = 2.7 V to 3.0 V 3
LOW Level Output Current IOL 8 mA VCC = 2.3 V to 2.7 V 3
Operating Free-Air Temperature TA -40 85 °C 3
Input Transition Rise or Fall Rate t/V 0 10 ns/V VIN from 0.8 V to 2.0 V, VCC = 3.0 V 3
DC Supply Voltage (absolute maximum) VCC -0.5 7 V 2
DC Input Voltage VI -0.5 7 V 2
DC Output Voltage VO -0.5 V Output in HIGH or LOW state (Note 1); max printed as VCC + 0.5 2
DC Input Diode Current IIK -50 mA VI < GND 2
DC Output Diode Current IOK -50 mA VO < GND 2
DC Output Diode Current IOK 50 mA VO > VCC 2
DC Output Source/Sink Current IO 50 mA 2
DC Supply Current ICC 100 mA Per supply pin 2
DC Ground Current IGND 100 mA Per ground pin 2
Storage Temperature Range TSTG -65 150 °C 2
HIGH Level Input Voltage VIH 1.7 V 2.3 V ≤ VCC ≤ 2.7 V; TA = −40 °C to +85 °C (Note 2) 3
HIGH Level Input Voltage VIH 2 V 2.7 V ≤ VCC ≤ 3.6 V; TA = −40 °C to +85 °C (Note 2) 3
LOW Level Input Voltage VIL 0.7 V 2.3 V ≤ VCC ≤ 2.7 V; TA = −40 °C to +85 °C (Note 2) 3
LOW Level Input Voltage VIL 0.8 V 2.7 V ≤ VCC ≤ 3.6 V; TA = −40 °C to +85 °C (Note 2) 3
HIGH Level Output Voltage VOH 1.8 V VCC = 2.3 V; IOH = −8 mA 3
HIGH Level Output Voltage VOH 2.2 V VCC = 2.7 V; IOH = −12 mA 3
HIGH Level Output Voltage VOH 2.4 V VCC = 3.0 V; IOH = −18 mA 3
LOW Level Output Voltage VOL 0.2 V 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 µA 3
LOW Level Output Voltage VOL 0.6 V VCC = 2.3 V; IOL = 8 mA 3
LOW Level Output Voltage VOL 0.4 V VCC = 2.7 V; IOL = 12 mA 3
LOW Level Output Voltage VOL 0.55 V VCC = 3.0 V; IOL = 24 mA 3
Power Off Leakage Current IOFF 10 µA VCC = 0, VIN = 5.5 V or VOUT = 5.5 V 3
Input Leakage Current IIN 5 µA VCC = 3.6 V, VIN = 5.5 V or GND 3
Quiescent Supply Current ICC 10 µA VCC = 3.6 V, VIN = 5.5 V or GND 3
Increase in ICC per Input ICC 500 µA 2.3 V ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 3
Propagation Delay Time LOW-to-HIGH (tPLH) tPLH 1.5 5.5 ns VCC = 3.3 V ± 0.3 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns 4
Propagation Delay Time LOW-to-HIGH (tPLH) tPLH 1.5 6.2 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns 4
Propagation Delay Time LOW-to-HIGH (tPLH) tPLH 1.5 6.6 ns VCC = 2.5 V ± 0.2 V; CL = 30 pF; RL = 500 Ω; tR = tF = 2.5 ns 4
Propagation Delay Time HIGH-to-LOW (tPHL) tPHL 1.5 5.5 ns VCC = 3.3 V ± 0.3 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns 4
Propagation Delay Time HIGH-to-LOW (tPHL) tPHL 1.5 6.2 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω; tR = tF = 2.5 ns 4
Propagation Delay Time HIGH-to-LOW (tPHL) tPHL 1.5 6.6 ns VCC = 2.5 V ± 0.2 V; CL = 30 pF; RL = 500 Ω; tR = tF = 2.5 ns 4
Output-to-Output Skew HIGH-to-LOW tOSHL 1 ns Note 3; any outputs switching in same direction 4
Output-to-Output Skew LOW-to-HIGH tOSLH 1 ns Note 3; any outputs switching in same direction 4
Dynamic LOW Peak Voltage VOLP 0.8 V VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25 °C (Note 4) 4
Dynamic LOW Peak Voltage VOLP 0.6 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V; TA = +25 °C (Note 4) 4
Dynamic LOW Valley Voltage VOLV -0.8 V VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V; TA = +25 °C (Note 4) 4
Dynamic LOW Valley Voltage VOLV -0.6 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V; TA = +25 °C (Note 4) 4
Input Capacitance CIN 7 pF VCC = 3.3 V, VI = 0 V or VCC 4
Output Capacitance COUT 8 pF VCC = 3.3 V, VI = 0 V or VCC 4
Power Dissipation Capacitance CPD 25 pF 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 4

CAD (KiCad official)

  • Symbol: MC74LCX00DTR2G
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: mc74lcx00dtr2g-etched.step / mc74lcx00dtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74lcx00dtr2g.step / mc74lcx00dtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (7 pp, sha256 74d7d652c48b8b15, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF