component
MC74HCT595ADTR2G
Public Made by Adomby adom
onsemi Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HCT595ADTR2G
onsemi · Shift Registers · TSSOP-16
MC74HCT595ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Noninverted, 3-state, latch parallel output QB, forced to high impedance when Output Enable is high. |
| 2 | QC | tri_state | Noninverted, 3-state, latch parallel output QC, forced to high impedance when Output Enable is high. |
| 3 | QD | tri_state | Noninverted, 3-state, latch parallel output QD, forced to high impedance when Output Enable is high. |
| 4 | QE | tri_state | Noninverted, 3-state, latch parallel output QE, forced to high impedance when Output Enable is high. |
| 5 | QF | tri_state | Noninverted, 3-state, latch parallel output QF, forced to high impedance when Output Enable is high. |
| 6 | QG | tri_state | Noninverted, 3-state, latch parallel output QG, forced to high impedance when Output Enable is high. |
| 7 | QH | tri_state | Noninverted, 3-state, latch parallel output QH, forced to high impedance when Output Enable is high. |
| 8 | GND | power_in | Ground reference; all DC voltages are referenced to GND. |
| 9 | SQH | output | Noninverted serial data output from the eighth stage of the 8-bit shift register; this output does not have three-state capability. |
| 10 | RESET | input | Active-low, asynchronous shift register reset input; a low resets only the shift register and does not affect the 8-bit latch. |
| 11 | SHIFT CLOCK | input | Shift register clock input; a low-to-high transition shifts the data at the Serial Input pin into the 8-bit shift register. |
| 12 | LATCH CLOCK | input | Storage latch clock input; a low-to-high transition latches the shift register data. |
| 13 | OUTPUT ENABLE | input | Active-low output enable; a low allows latch data to appear at QA-QH, while a high forces QA-QH into the high-impedance state without affecting SQH. |
| 14 | A | input | Serial data input shifted into the 8-bit serial shift register. |
| 15 | QA | tri_state | Noninverted, 3-state, latch parallel output QA, forced to high impedance when Output Enable is high. |
| 16 | VCC | power_in | Positive supply; recommended operating range 4.5 V to 5.5 V referenced to GND, absolute maximum 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | 3 | |||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | 3 | |||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | 3 | ||
| DC Output Current, per Pin | Iout | -35 | 35 | mA | 3 | ||
| DC Supply Current, VCC and GND Pins | ICC | -75 | 75 | mA | 3 | ||
| Power Dissipation in Still Air, TSSOP Package | PD | 450 | mW | TSSOP package, still air | 3 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds (plastic DIP, SOIC or TSSOP package) | 3 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 4.5 | 5.5 | V | 3 | ||
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | 3 | |||
| Operating Temperature Range, All Package Types | TA | -55 | 125 | °C | 3 | ||
| Input Rise/Fall Time | tr, tf | 0 | 500 | ns | Figure 1 | 3 | |
| Minimum High-Level Input Voltage | VIH | 2 | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; guaranteed at -55 to 25 C, 85 C and 125 C | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.8 | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC - 0.1 V; /Iout/ <= 20 uA; guaranteed at -55 to 25 C, 85 C and 125 C | 4 | ||
| Minimum High-Level Output Voltage, QA-QH | VOH | 4.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 20 uA; -55 to 125 C | 4 | ||
| Minimum High-Level Output Voltage, QA-QH | VOH | 3.98 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 6.0 mA; -55 to 25 C | 4 | ||
| Minimum High-Level Output Voltage, QA-QH | VOH | 3.84 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 6.0 mA; 85 C | 4 | ||
| Minimum High-Level Output Voltage, QA-QH | VOH | 3.7 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 6.0 mA; 125 C | 4 | ||
| Maximum Low-Level Output Voltage, QA-QH | VOL | 0.1 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 20 uA; -55 to 125 C | 4 | ||
| Maximum Low-Level Output Voltage, QA-QH | VOL | 0.26 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 6.0 mA; -55 to 25 C | 4 | ||
| Maximum Low-Level Output Voltage, QA-QH | VOL | 0.33 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 6.0 mA; 85 C | 4 | ||
| Maximum Low-Level Output Voltage, QA-QH | VOL | 0.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 6.0 mA; 125 C | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 4.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 20 uA; -55 to 125 C | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 3.98 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; -55 to 25 C | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 3.84 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; 85 C | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 3.7 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; 125 C | 4 | ||
| Maximum Low-Level Output Voltage, SQH | VOL | 0.1 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 20 uA; -55 to 125 C | 4 | ||
| Maximum Low-Level Output Voltage, SQH | VOL | 0.26 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; -55 to 25 C | 4 | ||
| Maximum Low-Level Output Voltage, SQH | VOL | 0.33 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; 85 C | 4 | ||
| Maximum Low-Level Output Voltage, SQH | VOL | 0.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ <= 4.0 mA; 125 C | 4 | ||
| Maximum Input Leakage Current | Iin | -0.1 | 0.1 | uA | VCC 5.5 V; Vin = VCC or GND; -55 to 25 C | 4 | |
| Maximum Input Leakage Current | Iin | -1 | 1 | uA | VCC 5.5 V; Vin = VCC or GND; 85 C | 4 | |
| Maximum Three-State Leakage Current, QA-QH | IOZ | -0.5 | 0.5 | uA | VCC 5.5 V; output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; -55 to 25 C | 4 | |
| Maximum Three-State Leakage Current, QA-QH | IOZ | -5 | 5 | uA | VCC 5.5 V; output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; 85 C | 4 | |
| Maximum Three-State Leakage Current, QA-QH | IOZ | -10 | 10 | uA | VCC 5.5 V; output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; 125 C | 4 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 4 | uA | VCC 5.5 V; Vin = VCC or GND; Iout = 0 A; -55 to 25 C | 4 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | uA | VCC 5.5 V; Vin = VCC or GND; Iout = 0 A; 85 C | 4 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | uA | VCC 5.5 V; Vin = VCC or GND; Iout = 0 A; 125 C | 4 | ||
| Additional Quiescent Supply Current | ICC | 2.9 | mA | VCC 5.5 V; Vin = 2.4 V any one input; Vin = VCC or GND other inputs; Iout = 0 A; -55 C column (column mapping inferred) | 4 | ||
| Additional Quiescent Supply Current | ICC | 2.4 | mA | VCC 5.5 V; Vin = 2.4 V any one input; Vin = VCC or GND other inputs; Iout = 0 A; 25 to 125 C column (column mapping inferred) | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 30 | MHz | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 1 and 7; -55 to 25 C (read as guaranteed minimum) | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 24 | MHz | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 1 and 7; 85 C (read as guaranteed minimum) | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 20 | MHz | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 1 and 7; 125 C (read as guaranteed minimum) | 5 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 5 | |||
| Maximum Three-State Output Capacitance (Output in High-Impedance State), QA-QH | Cout | 15 | pF | Output in high-impedance state, QA-QH | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL | 28 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 1 and 7; -55 to 25 C | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL | 35 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 1 and 7; 85 C | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL | 42 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 1 and 7; 125 C | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL | 28 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 3 and 7; -55 to 25 C | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL | 35 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 3 and 7; 85 C | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL | 42 | ns | VCC 4.5 to 5.5 V; CL = 50 pF; input tr = tf = 6.0 ns; Figures 3 and 7; 125 C | 5 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 10 | ns | VCC 4.5 to 5.5 V; Figure 5; -55 to 25 C | 5 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 13 | ns | VCC 4.5 to 5.5 V; Figure 5; 85 C | 5 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 15 | ns | VCC 4.5 to 5.5 V; Figure 5; 125 C | 5 | ||
| Minimum Hold Time, Shift Clock to Serial Data Input A | th | 5 | ns | VCC 4.5 to 5.5 V; Figure 5; -55 to 125 C | 5 | ||
| Minimum Pulse Width, Shift Clock | tw | 10 | ns | VCC 4.5 to 5.5 V; Figure 1; -55 to 25 C | 5 | ||
| Minimum Pulse Width, Shift Clock | tw | 13 | ns | VCC 4.5 to 5.5 V; Figure 1; 85 C | 5 | ||
| Minimum Pulse Width, Shift Clock | tw | 15 | ns | VCC 4.5 to 5.5 V; Figure 1; 125 C | 5 |
CAD (KiCad official)
- Symbol:
MC74HCT595ADTR2G - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hct595adtr2g-etched.step/mc74hct595adtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hct595adtr2g.step/mc74hct595adtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
55ae617580f618ca, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).