# MC74HCT595ADTG

**onsemi** · Shifting Register · TSSOP-16

MC74HCT595ADTG from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Noninverted, 3-state, latch output QB; it goes to high impedance when Output Enable is high. |
| 2 | QC | tri_state | Noninverted, 3-state, latch output QC; it goes to high impedance when Output Enable is high. |
| 3 | QD | tri_state | Noninverted, 3-state, latch output QD; it goes to high impedance when Output Enable is high. |
| 4 | QE | tri_state | Noninverted, 3-state, latch output QE; it goes to high impedance when Output Enable is high. |
| 5 | QF | tri_state | Noninverted, 3-state, latch output QF; it goes to high impedance when Output Enable is high. |
| 6 | QG | tri_state | Noninverted, 3-state, latch output QG; it goes to high impedance when Output Enable is high. |
| 7 | QH | tri_state | Noninverted, 3-state, latch output QH; it goes to high impedance when Output Enable is high. |
| 8 | GND | power_in | Ground pin (GND = pin 8); all DC voltages are referenced to GND and Vin and Vout must stay between GND and VCC. |
| 9 | SQH | output | Noninverted serial data output from the eighth stage of the 8-bit shift register; this output has no three-state capability. |
| 10 | RESET | input | Active-low, asynchronous reset of the shift register only; a low resets the shift register and does not affect the 8-bit latch. |
| 11 | SHIFT CLOCK | input | Shift register clock; a low-to-high transition shifts the data at the Serial Input pin into the 8-bit shift register. |
| 12 | LATCH CLOCK | input | Storage latch clock; a low-to-high transition latches the shift register data into the output latch. |
| 13 | OUTPUT ENABLE | input | Active-low output enable; a low lets latch data appear on QA-QH, and a high forces QA-QH into the high-impedance state. |
| 14 | A | input | Serial data input; the data on this pin is shifted into the 8-bit serial shift register. |
| 15 | QA | tri_state | Noninverted, 3-state, latch output QA; it goes to high impedance when Output Enable is high. |
| 16 | VCC | power_in | Positive supply (VCC = pin 16); the recommended operating range is 4.5 to 5.5 V referenced to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 |  | 7 | V | Referenced to GND | 3 |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 |  |  | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 |
| DC Output Voltage (Referenced to GND) | Vout | -0.5 |  |  | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 |
| DC Input Current, per Pin | Iin | -20 |  | 20 | mA | Per pin | 3 |
| DC Output Current, per Pin | Iout | -35 |  | 35 | mA | Per pin | 3 |
| DC Supply Current, VCC and GND Pins | ICC | -75 |  | 75 | mA | VCC and GND pins | 3 |
| Power Dissipation in Still Air | PD |  |  | 450 | mW | TSSOP package, still air | 3 |
| Storage Temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Lead Temperature | TL |  |  | 260 | °C | 1 mm from case for 10 seconds (plastic DIP, SOIC or TSSOP package) | 3 |
| DC Supply Voltage (Referenced to GND) | VCC | 4.5 |  | 5.5 | V | Referenced to GND | 3 |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 |  |  | V | Referenced to GND; upper limit printed as VCC | 3 |
| Operating Temperature Range, All Package Types | TA | -55 |  | 125 | °C | All package types | 3 |
| Input Rise/Fall Time | tr, tf | 0 |  | 500 | ns | Figure 1 | 3 |
| Minimum High-Level Input Voltage | VIH | 2 |  |  | V | Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5 to 5.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Low-Level Input Voltage | VIL |  |  | 0.8 | V | Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; VCC 4.5 to 5.5 V; guaranteed limit at 125 °C | 4 |
| Minimum High-Level Output Voltage, QA − QH | VOH | 4.4 |  |  | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Minimum High-Level Output Voltage, QA − QH | VOH | 3.7 |  |  | V | Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Low-Level Output Voltage, QA − QH | VOL |  |  | 0.1 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Low-Level Output Voltage, QA − QH | VOL |  |  | 0.4 | V | Vin = VIH or VIL; /Iout/ ≤ 6.0 mA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Minimum High-Level Output Voltage, SQH | VOH | 4.4 |  |  | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Minimum High-Level Output Voltage, SQH | VOH | 3.7 |  |  | V | Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Low-Level Output Voltage, SQH | VOL |  |  | 0.1 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Low-Level Output Voltage, SQH | VOL |  |  | 0.4 | V | Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC 4.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Input Leakage Current | Iin | -1 |  | 1 | µA | Vin = VCC or GND; VCC 5.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Three-State Leakage Current, QA − QH | IOZ | -10 |  | 10 | µA | Output in high-impedance state; Vin = VIL or VIH; Vout = VCC or GND; VCC 5.5 V; guaranteed limit at 125 °C | 4 |
| Maximum Quiescent Supply Current (per Package) | ICC |  |  | 160 | µA | Vin = VCC or GND; Iout = 0 µA; VCC 5.5 V; guaranteed limit at 125 °C | 4 |
| Additional Quiescent Supply Current | ICC |  |  | 2.9 | mA | Vin = 2.4 V any one input; Vin = VCC or GND other inputs; Iout = 0 A; VCC 5.5 V; ≥ −55 °C column | 4 |
| Additional Quiescent Supply Current | ICC |  |  | 2.4 | mA | Vin = 2.4 V any one input; Vin = VCC or GND other inputs; Iout = 0 A; VCC 5.5 V; 25 to 125 °C column | 4 |
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 20 |  |  | MHz | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; 50% duty cycle; Figures 1 and 7; guaranteed limit at 125 °C | 5 |
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL |  |  | 42 | ns | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figures 1 and 7; guaranteed limit at 125 °C | 5 |
| Maximum Propagation Delay, Reset to SQH | tPHL |  |  | 44 | ns | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figures 2 and 7; guaranteed limit at 125 °C | 5 |
| Maximum Propagation Delay, Latch Clock to QA − QH | tPLH, tPHL |  |  | 42 | ns | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figures 3 and 7; guaranteed limit at 125 °C | 5 |
| Maximum Propagation Delay, Output Enable to QA − QH (disable) | tPLZ, tPHZ |  |  | 45 | ns | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figures 4 and 8; guaranteed limit at 125 °C | 5 |
| Maximum Propagation Delay, Output Enable to QA − QH (enable) | tPZL, tPZH |  |  | 41 | ns | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figures 4 and 8; guaranteed limit at 125 °C | 5 |
| Maximum Output Transition Time, QA − QH | tTLH, tTHL |  |  | 18 | ns | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figures 3 and 7; guaranteed limit at 125 °C | 5 |
| Maximum Output Transition Time, SQH | tTLH, tTHL |  |  | 22 | ns | CL = 50 pF; input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figures 1 and 7; guaranteed limit at 125 °C | 5 |
| Maximum Input Capacitance | Cin |  |  | 10 | pF |  | 5 |
| Maximum Three-State Output Capacitance (Output in High-Impedance State), QA − QH | Cout |  |  | 15 | pF | Output in high-impedance state | 5 |
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 15 |  |  | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 5; guaranteed limit at 125 °C | 5 |
| Minimum Setup Time, Shift Clock to Latch Clock | tsu | 22 |  |  | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 6; guaranteed limit at 125 °C | 5 |
| Minimum Hold Time, Shift Clock to Serial Data Input A | th | 5 |  |  | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 5; guaranteed limit at 125 °C | 5 |
| Minimum Recovery Time, Reset Inactive to Shift Clock | trec | 15 |  |  | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 2; guaranteed limit at 125 °C | 5 |
| Minimum Pulse Width, Reset | tw | 18 |  |  | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 2; guaranteed limit at 125 °C | 5 |
| Minimum Pulse Width, Shift Clock | tw | 15 |  |  | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 1; guaranteed limit at 125 °C | 5 |
| Minimum Pulse Width, Latch Clock | tw | 15 |  |  | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 6; guaranteed limit at 125 °C | 5 |
| Maximum Input Rise and Fall Times | tr, tf |  |  | 500 | ns | Input tr = tf = 6.0 ns; VCC 4.5 to 5.5 V; Figure 1; guaranteed limit at 125 °C | 5 |

## CAD (KiCad official)

- Symbol: `MC74HCT595ADTG`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `mc74hct595adtg-etched.step` / `mc74hct595adtg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hct595adtg.step` / `mc74hct595adtg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hct595adt-d.pdf) (12 pp, sha256 `ebb8ded30ddb2e25`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mc74hct595adtg-datasheet.pdf)