component
MC74HCT595ADG
Public Made by Adomby adom
onsemi Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"description": "onsemi Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"logic ics",
"mc74hct595adg",
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"component": {
"mpn": "MC74HCT595ADG",
"manufacturer": "onsemi",
"package": "SOIC-16",
"pin_count": 16,
"category": "Logic ICs",
"subcategory": "Registers",
"datasheet": "https://www.onsemi.com/pdf/datasheet/mc74hct595a-d.pdf",
"parts": {
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"footprint": "mc74hct595adg.kicad_mod",
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"model_3d_step_plain": "mc74hct595adg.step",
"lbr": "mc74hct595adg.lbr"
},
"distributor_links": {
"lcsc": "C906873",
"digikey": "MC74HCT595ADGOS-ND",
"mouser": "863-MC74HCT595ADG"
},
"distributor_check": {
"checked_at": "2026-10-28T22:53:02Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "MC74HCT595ADGOS-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "863-MC74HCT595ADG",
"status": "found"
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},
"pins": [
{
"number": "1",
"name": "QB",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output B; forced to high impedance when Output Enable is high."
},
{
"number": "2",
"name": "QC",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output C; forced to high impedance when Output Enable is high."
},
{
"number": "3",
"name": "QD",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output D; forced to high impedance when Output Enable is high."
},
{
"number": "4",
"name": "QE",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output E; forced to high impedance when Output Enable is high."
},
{
"number": "5",
"name": "QF",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output F; forced to high impedance when Output Enable is high."
},
{
"number": "6",
"name": "QG",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output G; forced to high impedance when Output Enable is high."
},
{
"number": "7",
"name": "QH",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output H; forced to high impedance when Output Enable is high."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference pin; all voltages are referenced to GND, and VCC must be held between 4.5 and 5.5 V relative to it."
},
{
"number": "9",
"name": "SQH",
"type": "output",
"description": "Noninverted serial data output from the eighth shift register stage; it does not have three-state capability."
},
{
"number": "10",
"name": "RESET",
"type": "input",
"description": "Active-low asynchronous reset for the shift register only; a low resets the shift register and does not affect the 8-bit latch."
},
{
"number": "11",
"name": "SHIFT CLOCK",
"type": "input",
"description": "Shift register clock; a low-to-high transition shifts the data at the serial input A into the 8-bit shift register."
},
{
"number": "12",
"name": "LATCH CLOCK",
"type": "input",
"description": "Storage latch clock; a low-to-high transition latches the shift register data into the 8-bit latch."
},
{
"number": "13",
"name": "OUTPUT ENABLE",
"type": "input",
"description": "Active-low output enable; a low lets the latch data appear on QA-QH, while a high forces QA-QH into high impedance without affecting SQH."
},
{
"number": "14",
"name": "A",
"type": "input",
"description": "Serial data input shifted into the 8-bit shift register on each low-to-high shift clock transition."
},
{
"number": "15",
"name": "QA",
"type": "tri_state",
"description": "Noninverted, three-state parallel latch output A; forced to high impedance when Output Enable is high."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Positive supply pin; the recommended DC supply range is 4.5 to 5.5 V referenced to GND."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The PIN ASSIGNMENT graphic text in the extraction is scrambled. The pin-to-name mapping was taken fr; The datasheet covers SOIC-16 (DG and DR2G suffixes) and TSSOP-16 (DT suffix). MC74HCT595ADG is the S"
],
"pages_sent": 12,
"cost_usd": 0.0774,
"at": "2026-10-28T22:52:48"
},
"datasheet": {
"url": "https://www.onsemi.com/pdf/datasheet/mc74hct595a-d.pdf",
"pages": 12,
"sha256": "a09e1caabec3fe23",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
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"models_3d": [
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"file": "mc74hct595adg.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
9.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
"checked": "2026-10-28",
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{
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"extents_mm": [
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"sha256": "da064fe5c041608c4569990aa090f73d290def21d7caeb9a22c55fd24214f0df",
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],
"package_dims": {
"package_code": "SOIC-16 (CASE 751B-05)",
"source_page": 10,
"D": {
"nom_mm": 9.9,
"range_mm": [
9.8,
10.0
]
},
"E1": {
"nom_mm": 3.9,
"range_mm": [
3.8,
4.0
]
},
"E": {
"nom_mm": 6.0,
"range_mm": [
5.8,
6.2
]
},
"e": {
"nom_mm": 1.27,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 1.55,
"range_mm": [
1.35,
1.75
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},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "mc74hct595adg.step",
"verdict": "PASS",
"reasons": [
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}
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}