component
MC74HCT573ADWG
Public Made by Adomby adom
onsemi Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MC74HCT573ADWG
onsemi · Latches · SOIC-20-300mil
MC74HCT573ADWG from onsemi, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTPUT ENABLE | input | When Output Enable is high, all device outputs are forced to the high-impedance state, and it does not affect the latch contents. |
| 2 | D0 | input | Data input D0 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 3 | D1 | input | Data input D1 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 4 | D2 | input | Data input D2 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 5 | D3 | input | Data input D3 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 6 | D4 | input | Data input D4 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 7 | D5 | input | Data input D5 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 8 | D6 | input | Data input D6 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 9 | D7 | input | Data input D7 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 10 | GND | power_in | Ground reference for the device; all voltages are referenced to this pin. |
| 11 | LATCH ENABLE | input | While Latch Enable is high the latches are transparent to data, and data is latched when it goes low. |
| 12 | Q7 | tri_state | Noninverting three-state latch output Q7, which goes to high impedance when Output Enable is high. |
| 13 | Q6 | tri_state | Noninverting three-state latch output Q6, which goes to high impedance when Output Enable is high. |
| 14 | Q5 | tri_state | Noninverting three-state latch output Q5, which goes to high impedance when Output Enable is high. |
| 15 | Q4 | tri_state | Noninverting three-state latch output Q4, which goes to high impedance when Output Enable is high. |
| 16 | Q3 | tri_state | Noninverting three-state latch output Q3, which goes to high impedance when Output Enable is high. |
| 17 | Q2 | tri_state | Noninverting three-state latch output Q2, which goes to high impedance when Output Enable is high. |
| 18 | Q1 | tri_state | Noninverting three-state latch output Q1, which goes to high impedance when Output Enable is high. |
| 19 | Q0 | tri_state | Noninverting three-state latch output Q0, which goes to high impedance when Output Enable is high. |
| 20 | VCC | power_in | Positive supply pin, specified at 4.5 to 5.5 V DC referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-20-300mil |
| Category | Logic ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 4.5 | 5.5 | V | 2 | ||
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Referenced to GND; max printed as VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | C | 2 | ||
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | Figure 1 | 2 | |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Referenced to GND; max printed as VCC + 0.5 | 2 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Referenced to GND; max printed as VCC + 0.5 | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | per pin | 2 | |
| DC Output Current, per Pin | Iout | -25 | 25 | mA | per pin | 2 | |
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | VCC and GND pins | 2 | |
| Power Dissipation in Still Air | PD | 500 | mW | SOIC Package (TSSOP 450 mW omitted, not this package) | 2 | ||
| Storage Temperature | Tstg | -65 | 150 | C | 2 | ||
| Lead Temperature, 1 mm from Case for 10 Seconds | TL | 260 | C | TSSOP or SOIC Package | 2 | ||
| Minimum High-Level Input Voltage | VIH | 2 | V | VCC=4.5 V; Vout=0.1 V or VCC-0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.8 | V | VCC=4.5 V; Vout=0.1 V or VCC-0.1 V; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.4 | V | VCC=5.5 V; Vin=VIH or VIL; /Iout/ ≤ 20 µA | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 6.0 mA (worst case of printed temperature columns) | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 20 µA | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 6.0 mA (worst case of printed temperature columns) | 3 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC=5.5 V; Vin=VCC or GND | 3 | |
| Maximum Three-State Leakage Current | IOZ | -10 | 10 | µA | VCC=5.5 V; Output in High-Impedance State; Vin=VIL or VIH; Vout=VCC or GND (worst case of printed temperature columns) | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | VCC=5.5 V; Vin=VCC or GND; Iout ≤ 0 A (worst case of printed temperature columns) | 3 | ||
| Additional Quiescent Supply Current | ΔICC | 2.9 | mA | VCC=5.5 V; Vin=2.4 V, any one input; Vin=VCC or GND, other inputs; Iout=0 A | 3 | ||
| Maximum Propagation Delay, Input D to Output Q | tPLH, tPHL | 45 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 1 and 5 | 3 | ||
| Maximum Propagation Delay, Latch Enable to Q | tPLH, tPHL | 45 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 2 and 5 | 3 | ||
| Maximum Propagation Delay, Output Enable to Q | TPLZ, TPHZ | 42 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 3 and 6 | 3 | ||
| Maximum Output Transition Time, any Output | tTLH, tTHL | 18 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 1 and 5 | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 | |||
| Maximum Three-State Output Capacitance | Cout | 15 | pF | Output in High-Impedance State | 3 | ||
| Minimum Setup Time, Input D to Latch Enable | tsu | 15 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 4 (worst case of printed temperature columns) | 3 | ||
| Minimum Hold Time, Latch Enable to Input D | th | 5 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 4 | 3 | ||
| Minimum Pulse Width, Latch Enable | tw | 22 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 2 (worst case of printed temperature columns) | 3 | ||
| Maximum Input Rise and Fall Times | tr, tf | 500 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 1 | 3 | ||
| Typical Power Dissipation Capacitance (Per Enabled Output) | CPD | 48 | pF | Typical @ 25°C, VCC=5.0 V | 3 |
CAD (KiCad official)
- Symbol:
MC74HCT573ADWG - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
mc74hct573adwg-etched.step/mc74hct573adwg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hct573adwg.step/mc74hct573adwg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (6 pp, sha256
cdf07b1d5992d580, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HCT573ADWG
**onsemi** · Latches · SOIC-20-300mil
MC74HCT573ADWG from onsemi, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTPUT ENABLE | input | When Output Enable is high, all device outputs are forced to the high-impedance state, and it does not affect the latch contents. |
| 2 | D0 | input | Data input D0 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 3 | D1 | input | Data input D1 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 4 | D2 | input | Data input D2 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 5 | D3 | input | Data input D3 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 6 | D4 | input | Data input D4 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 7 | D5 | input | Data input D5 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 8 | D6 | input | Data input D6 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 9 | D7 | input | Data input D7 to the octal latch, which must meet the setup and hold times relative to Latch Enable. |
| 10 | GND | power_in | Ground reference for the device; all voltages are referenced to this pin. |
| 11 | LATCH ENABLE | input | While Latch Enable is high the latches are transparent to data, and data is latched when it goes low. |
| 12 | Q7 | tri_state | Noninverting three-state latch output Q7, which goes to high impedance when Output Enable is high. |
| 13 | Q6 | tri_state | Noninverting three-state latch output Q6, which goes to high impedance when Output Enable is high. |
| 14 | Q5 | tri_state | Noninverting three-state latch output Q5, which goes to high impedance when Output Enable is high. |
| 15 | Q4 | tri_state | Noninverting three-state latch output Q4, which goes to high impedance when Output Enable is high. |
| 16 | Q3 | tri_state | Noninverting three-state latch output Q3, which goes to high impedance when Output Enable is high. |
| 17 | Q2 | tri_state | Noninverting three-state latch output Q2, which goes to high impedance when Output Enable is high. |
| 18 | Q1 | tri_state | Noninverting three-state latch output Q1, which goes to high impedance when Output Enable is high. |
| 19 | Q0 | tri_state | Noninverting three-state latch output Q0, which goes to high impedance when Output Enable is high. |
| 20 | VCC | power_in | Positive supply pin, specified at 4.5 to 5.5 V DC referenced to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-20-300mil |
| Category | Logic ICs |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 4.5 | | 5.5 | V | | 2 |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | | | V | Referenced to GND; max printed as VCC | 2 |
| Operating Temperature, All Package Types | TA | -55 | | 125 | C | | 2 |
| Input Rise and Fall Time | tr, tf | 0 | | 500 | ns | Figure 1 | 2 |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | | 7 | V | Referenced to GND | 2 |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | | | V | Referenced to GND; max printed as VCC + 0.5 | 2 |
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | | | V | Referenced to GND; max printed as VCC + 0.5 | 2 |
| DC Input Current, per Pin | Iin | -20 | | 20 | mA | per pin | 2 |
| DC Output Current, per Pin | Iout | -25 | | 25 | mA | per pin | 2 |
| DC Supply Current, VCC and GND Pins | ICC | -50 | | 50 | mA | VCC and GND pins | 2 |
| Power Dissipation in Still Air | PD | | | 500 | mW | SOIC Package (TSSOP 450 mW omitted, not this package) | 2 |
| Storage Temperature | Tstg | -65 | | 150 | C | | 2 |
| Lead Temperature, 1 mm from Case for 10 Seconds | TL | | | 260 | C | TSSOP or SOIC Package | 2 |
| Minimum High-Level Input Voltage | VIH | 2 | | | V | VCC=4.5 V; Vout=0.1 V or VCC-0.1 V; /Iout/ ≤ 20 µA | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 0.8 | V | VCC=4.5 V; Vout=0.1 V or VCC-0.1 V; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Output Voltage | VOH | 5.4 | | | V | VCC=5.5 V; Vin=VIH or VIL; /Iout/ ≤ 20 µA | 3 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 6.0 mA (worst case of printed temperature columns) | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 20 µA | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC=4.5 V; Vin=VIH or VIL; /Iout/ ≤ 6.0 mA (worst case of printed temperature columns) | 3 |
| Maximum Input Leakage Current | Iin | -1 | | 1 | µA | VCC=5.5 V; Vin=VCC or GND | 3 |
| Maximum Three-State Leakage Current | IOZ | -10 | | 10 | µA | VCC=5.5 V; Output in High-Impedance State; Vin=VIL or VIH; Vout=VCC or GND (worst case of printed temperature columns) | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 160 | µA | VCC=5.5 V; Vin=VCC or GND; Iout ≤ 0 A (worst case of printed temperature columns) | 3 |
| Additional Quiescent Supply Current | ΔICC | | | 2.9 | mA | VCC=5.5 V; Vin=2.4 V, any one input; Vin=VCC or GND, other inputs; Iout=0 A | 3 |
| Maximum Propagation Delay, Input D to Output Q | tPLH, tPHL | | | 45 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 1 and 5 | 3 |
| Maximum Propagation Delay, Latch Enable to Q | tPLH, tPHL | | | 45 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 2 and 5 | 3 |
| Maximum Propagation Delay, Output Enable to Q | TPLZ, TPHZ | | | 42 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 3 and 6 | 3 |
| Maximum Output Transition Time, any Output | tTLH, tTHL | | | 18 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figures 1 and 5 | 3 |
| Maximum Input Capacitance | Cin | | | 10 | pF | | 3 |
| Maximum Three-State Output Capacitance | Cout | | | 15 | pF | Output in High-Impedance State | 3 |
| Minimum Setup Time, Input D to Latch Enable | tsu | 15 | | | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 4 (worst case of printed temperature columns) | 3 |
| Minimum Hold Time, Latch Enable to Input D | th | 5 | | | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 4 | 3 |
| Minimum Pulse Width, Latch Enable | tw | 22 | | | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 2 (worst case of printed temperature columns) | 3 |
| Maximum Input Rise and Fall Times | tr, tf | | | 500 | ns | VCC=5.0 V ±10%, CL=50 pF, Input tr=tf=6.0 ns; Figure 1 | 3 |
| Typical Power Dissipation Capacitance (Per Enabled Output) | CPD | | 48 | | pF | Typical @ 25°C, VCC=5.0 V | 3 |
## CAD (KiCad official)
- Symbol: `MC74HCT573ADWG`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `mc74hct573adwg-etched.step` / `mc74hct573adwg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hct573adwg.step` / `mc74hct573adwg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hct573adw-d.pdf) (6 pp, sha256 `cdf07b1d5992d580`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hct573adwg-datasheet.pdf)