component
MC74HCT32ADR2G
Public Made by Adomby adom
onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74HCT32ADR2G
onsemi · Logic Gates · SOIC-14
MC74HCT32ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A of gate 1 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 2 | B1 | input | Input B of gate 1 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 3 | Y1 | output | Output of gate 1 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 4 | A2 | input | Input A of gate 2 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 5 | B2 | input | Input B of gate 2 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 6 | Y2 | output | Output of gate 2 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 7 | GND | power_in | Ground reference for all voltages; the datasheet references VCC range 2.0 V to 6.0 V to this pin. |
| 8 | Y3 | output | Output of gate 3 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 9 | A3 | input | Input A of gate 3 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 10 | B3 | input | Input B of gate 3 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 11 | Y4 | output | Output of gate 4 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 12 | A4 | input | Input A of gate 4 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 13 | B4 | input | Input B of gate 4 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply; the datasheet recommends a DC supply voltage of 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Referenced to GND; printed upper limit is VCC +0.5 V | 2 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Referenced to GND; printed upper limit is VCC +0.5 V | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | Per pin | 2 | |
| DC Output Current, per Pin | Iout | -25 | 25 | mA | Per pin | 2 | |
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | VCC and GND pins | 2 | |
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | Still air; SOIC package | 2 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds; plastic DIP, SOIC or TSSOP package | 2 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Referenced to GND; printed upper limit is VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | 2 | ||
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 2 | |
| Minimum High-Level Input Voltage | VIH | 2 | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 | ||
| Maximum Low-Level Input Voltage | VIL | 0.8 | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 5.4 | V | VCC 5.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.98 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; −55 to 25 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.84 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤85 °C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤125 °C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.26 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; −55 to 25 °C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.33 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤85 °C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤125 °C | 3 | ||
| Maximum Input Leakage Current | Iin | -0.1 | 0.1 | µA | VCC 5.5 V; Vin = VCC or GND; −55 to 25 °C | 3 | |
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC 5.5 V; Vin = VCC or GND; ≤85 °C | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 1 | µA | VCC 5.5 V; Vin = VCC or GND; Iout = 0A; −55 to 25 °C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 10 | µA | VCC 5.5 V; Vin = VCC or GND; Iout = 0A; ≤85 °C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | VCC 5.5 V; Vin = VCC or GND; Iout = 0A; ≤125 °C | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 15 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; −55 to 25 °C | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 19 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤85 °C | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 22 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤125 °C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 15 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; −55 to 25 °C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 19 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤85 °C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 22 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤125 °C | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 | |||
| Power Dissipation Capacitance (Per Buffer) | CPD | 20 | pF | Typical @ 25°C, VCC = 5.0 V, VEE = 0 V | 3 |
CAD (KiCad official)
- Symbol:
MC74HCT32ADR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hct32adr2g-etched.step/mc74hct32adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hct32adr2g.step/mc74hct32adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
4014331f9660fdd8, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HCT32ADR2G
**onsemi** · Logic Gates · SOIC-14
MC74HCT32ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A of gate 1 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 2 | B1 | input | Input B of gate 1 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 3 | Y1 | output | Output of gate 1 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 4 | A2 | input | Input A of gate 2 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 5 | B2 | input | Input B of gate 2 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 6 | Y2 | output | Output of gate 2 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 7 | GND | power_in | Ground reference for all voltages; the datasheet references VCC range 2.0 V to 6.0 V to this pin. |
| 8 | Y3 | output | Output of gate 3 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 9 | A3 | input | Input A of gate 3 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 10 | B3 | input | Input B of gate 3 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 11 | Y4 | output | Output of gate 4 (Y = A + B); output voltage must stay between GND and VCC, and unused outputs must be left open. |
| 12 | A4 | input | Input A of gate 4 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 13 | B4 | input | Input B of gate 4 (Y = A + B); input voltage must stay between GND and VCC, and unused inputs must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply; the datasheet recommends a DC supply voltage of 2.0 V to 6.0 V referenced to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | | 7 | V | Referenced to GND | 2 |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | | | V | Referenced to GND; printed upper limit is VCC +0.5 V | 2 |
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | | | V | Referenced to GND; printed upper limit is VCC +0.5 V | 2 |
| DC Input Current, per Pin | Iin | -20 | | 20 | mA | Per pin | 2 |
| DC Output Current, per Pin | Iout | -25 | | 25 | mA | Per pin | 2 |
| DC Supply Current, VCC and GND Pins | ICC | -50 | | 50 | mA | VCC and GND pins | 2 |
| Power Dissipation in Still Air, SOIC Package | PD | | | 500 | mW | Still air; SOIC package | 2 |
| Storage Temperature | Tstg | -65 | | 150 | °C | | 2 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds; plastic DIP, SOIC or TSSOP package | 2 |
| DC Supply Voltage (Referenced to GND) | VCC | 2 | | 6 | V | Referenced to GND | 2 |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | | | V | Referenced to GND; printed upper limit is VCC | 2 |
| Operating Temperature, All Package Types | TA | -55 | | 125 | °C | | 2 |
| Input Rise and Fall Time | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V (Figure 1) | 2 |
| Input Rise and Fall Time | tr, tf | 0 | | 500 | ns | VCC = 4.5 V (Figure 1) | 2 |
| Input Rise and Fall Time | tr, tf | 0 | | 400 | ns | VCC = 6.0 V (Figure 1) | 2 |
| Minimum High-Level Input Voltage | VIH | 2 | | | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 |
| Maximum Low-Level Input Voltage | VIL | | | 0.8 | V | VCC 4.5 to 5.5 V; Vout = 0.1 V or VCC − 0.1 V; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 5.4 | | | V | VCC 5.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.98 | | | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; −55 to 25 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.84 | | | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤85 °C | 3 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤125 °C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 20 µA; guaranteed −55 to 125 °C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.26 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; −55 to 25 °C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.33 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤85 °C | 3 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; ≤125 °C | 3 |
| Maximum Input Leakage Current | Iin | -0.1 | | 0.1 | µA | VCC 5.5 V; Vin = VCC or GND; −55 to 25 °C | 3 |
| Maximum Input Leakage Current | Iin | -1 | | 1 | µA | VCC 5.5 V; Vin = VCC or GND; ≤85 °C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 1 | µA | VCC 5.5 V; Vin = VCC or GND; Iout = 0A; −55 to 25 °C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 10 | µA | VCC 5.5 V; Vin = VCC or GND; Iout = 0A; ≤85 °C | 3 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 40 | µA | VCC 5.5 V; Vin = VCC or GND; Iout = 0A; ≤125 °C | 3 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 15 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; −55 to 25 °C | 3 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 19 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤85 °C | 3 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 22 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤125 °C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 15 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; −55 to 25 °C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 19 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤85 °C | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 22 | ns | CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%; Figures 1 and 2; ≤125 °C | 3 |
| Maximum Input Capacitance | Cin | | | 10 | pF | | 3 |
| Power Dissipation Capacitance (Per Buffer) | CPD | | 20 | | pF | Typical @ 25°C, VCC = 5.0 V, VEE = 0 V | 3 |
## CAD (KiCad official)
- Symbol: `MC74HCT32ADR2G`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mc74hct32adr2g-etched.step` / `mc74hct32adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hct32adr2g.step` / `mc74hct32adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hct32a-d.pdf) (8 pp, sha256 `4014331f9660fdd8`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hct32adr2g-datasheet.pdf)