component
MC74HCT132ADR2G
Public Made by Adomby adom
onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MC74HCT132ADR2G
onsemi · Logic Gates · SOIC-14
MC74HCT132ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A1 of NAND gate 1 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 2 | B1 | input | Input B1 of NAND gate 1 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 3 | Y1 | output | Output Y1 of NAND gate 1, Y = AB, rated for 10 LSTTL loads. |
| 4 | A2 | input | Input A2 of NAND gate 2 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 5 | B2 | input | Input B2 of NAND gate 2 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 6 | Y2 | output | Output Y2 of NAND gate 2, Y = AB, rated for 10 LSTTL loads. |
| 7 | GND | power_in | Ground reference pin; all voltages are referenced to GND and the supply range is 2.0 V to 6.0 V with respect to it. |
| 8 | Y3 | output | Output Y3 of NAND gate 3, Y = AB, rated for 10 LSTTL loads. |
| 9 | A3 | input | Input A3 of NAND gate 3 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 10 | B3 | input | Input B3 of NAND gate 3 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 11 | Y4 | output | Output Y4 of NAND gate 4, Y = AB, rated for 10 LSTTL loads. |
| 12 | A4 | input | Input A4 of NAND gate 4 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 13 | B4 | input | Input B4 of NAND gate 4 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 14 | VCC | power_in | Positive DC supply, recommended operating range 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | 3 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | 3 | ||
| DC Input Voltage, Output Voltage (Referenced to GND) | VIN, VOUT | 0 | V | Upper limit printed as VCC | 3 | ||
| Positive DC Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| Digital Input Voltage | VIN | -0.5 | 7 | V | 3 | ||
| DC Output Voltage | VOUT | -0.5 | 7 | V | Output in 3-State | 3 | |
| DC Output Voltage | VOUT | -0.5 | V | Output in High or Low State; upper limit printed as VCC + 0.5 V | 3 | ||
| Input Diode Current | IIK | 20 | mA | 3 | |||
| Output Diode Current | IOK | 20 | mA | 3 | |||
| DC Output Current, per Pin | IOUT | 25 | mA | 3 | |||
| DC Supply Current, VCC and GND Pins | ICC | 75 | mA | 3 | |||
| DC Ground Current per Ground Pin | IGND | 75 | mA | 3 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 3 | ||
| Junction Temperature Under Bias | TJ | 150 | °C | 3 | |||
| ESD Withstand Voltage | VESD | 2000 | V | Human Body Model | 3 | ||
| ESD Withstand Voltage | VESD | 100 | V | Machine Model | 3 | ||
| ESD Withstand Voltage | VESD | 500 | V | Charged Device Model | 3 | ||
| Latch-Up Performance | ILatch-Up | 300 | mA | Above VCC and below GND at 85°C | 3 | ||
| Thermal Resistance, Junction to Ambient | θJA | 125 | °C/W | 14-SOIC | 3 | ||
| Power Dissipation in Still Air at 85°C | PD | 500 | mW | SOIC | 3 | ||
| Maximum Positive-Going Input Threshold Voltage | VT+max | 1.9 | V | VCC 4.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Maximum Positive-Going Input Threshold Voltage | VT+max | 2.1 | V | VCC 5.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum Positive-Going Input Threshold Voltage | VT+min | 1.2 | V | VCC 4.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum Positive-Going Input Threshold Voltage | VT+min | 1.4 | V | VCC 5.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Maximum Negative-Going Input Threshold Voltage | VT-max | 1.2 | V | VCC 4.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Maximum Negative-Going Input Threshold Voltage | VT-max | 1.4 | V | VCC 5.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum Negative-Going Input Threshold Voltage | VT-min | 0.5 | V | VCC 4.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum Negative-Going Input Threshold Voltage | VT-min | 0.6 | V | VCC 5.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum Hysteresis Voltage | VHmin | 0.4 | V | VCC 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC 4.5 V; VIN ≥ VT−min or VT+max; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.4 | V | VCC 5.5 V; VIN ≥ VT−min or VT+max; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC 4.5 V; /IOUT/ = 4.0 mA; 125°C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC 4.5 V; VIN ≥ VT+max; /IOUT/ ≤ 20 µA; 125°C | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC 4.5 V; VIN ≥ VT+max; /IOUT/ = 4.0 mA; 125°C | 4 | ||
| Maximum Input Leakage Current | IIN | 1 | µA | VCC 5.5 V; VIN = VCC or GND; 125°C | 4 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | VCC 5.5 V; VIN = VCC or GND; IOUT = 0 µA; 125°C | 4 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 38 | ns | VCC 5.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; 125°C | 4 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 22 | ns | VCC 5.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; 125°C | 4 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 4 | |||
| Power Dissipation Capacitance (per Gate) | CPD | 24 | pF | Typical at 25°C, VCC 5.0 V; Note 8 | 4 |
CAD (KiCad official)
- Symbol:
MC74HCT132ADR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hct132adr2g-etched.step/mc74hct132adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hct132adr2g.step/mc74hct132adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (9 pp, sha256
e8a59d2445bfc45e, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HCT132ADR2G
**onsemi** · Logic Gates · SOIC-14
MC74HCT132ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A1 of NAND gate 1 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 2 | B1 | input | Input B1 of NAND gate 1 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 3 | Y1 | output | Output Y1 of NAND gate 1, Y = AB, rated for 10 LSTTL loads. |
| 4 | A2 | input | Input A2 of NAND gate 2 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 5 | B2 | input | Input B2 of NAND gate 2 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 6 | Y2 | output | Output Y2 of NAND gate 2, Y = AB, rated for 10 LSTTL loads. |
| 7 | GND | power_in | Ground reference pin; all voltages are referenced to GND and the supply range is 2.0 V to 6.0 V with respect to it. |
| 8 | Y3 | output | Output Y3 of NAND gate 3, Y = AB, rated for 10 LSTTL loads. |
| 9 | A3 | input | Input A3 of NAND gate 3 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 10 | B3 | input | Input B3 of NAND gate 3 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 11 | Y4 | output | Output Y4 of NAND gate 4, Y = AB, rated for 10 LSTTL loads. |
| 12 | A4 | input | Input A4 of NAND gate 4 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 13 | B4 | input | Input B4 of NAND gate 4 (Schmitt-trigger input); unused inputs may not be left open and must be tied to a valid high or low logic level. |
| 14 | VCC | power_in | Positive DC supply, recommended operating range 2.0 V to 6.0 V referenced to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | | 6 | V | | 3 |
| Operating Temperature, All Package Types | TA | -55 | | 125 | °C | | 3 |
| DC Input Voltage, Output Voltage (Referenced to GND) | VIN, VOUT | 0 | | | V | Upper limit printed as VCC | 3 |
| Positive DC Supply Voltage | VCC | -0.5 | | 7 | V | | 3 |
| Digital Input Voltage | VIN | -0.5 | | 7 | V | | 3 |
| DC Output Voltage | VOUT | -0.5 | | 7 | V | Output in 3-State | 3 |
| DC Output Voltage | VOUT | -0.5 | | | V | Output in High or Low State; upper limit printed as VCC + 0.5 V | 3 |
| Input Diode Current | IIK | | | 20 | mA | | 3 |
| Output Diode Current | IOK | | | 20 | mA | | 3 |
| DC Output Current, per Pin | IOUT | | | 25 | mA | | 3 |
| DC Supply Current, VCC and GND Pins | ICC | | | 75 | mA | | 3 |
| DC Ground Current per Ground Pin | IGND | | | 75 | mA | | 3 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 3 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds | 3 |
| Junction Temperature Under Bias | TJ | | | 150 | °C | | 3 |
| ESD Withstand Voltage | VESD | | | 2000 | V | Human Body Model | 3 |
| ESD Withstand Voltage | VESD | | | 100 | V | Machine Model | 3 |
| ESD Withstand Voltage | VESD | | | 500 | V | Charged Device Model | 3 |
| Latch-Up Performance | ILatch-Up | | | 300 | mA | Above VCC and below GND at 85°C | 3 |
| Thermal Resistance, Junction to Ambient | θJA | | | 125 | °C/W | 14-SOIC | 3 |
| Power Dissipation in Still Air at 85°C | PD | | | 500 | mW | SOIC | 3 |
| Maximum Positive-Going Input Threshold Voltage | VT+max | | | 1.9 | V | VCC 4.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Maximum Positive-Going Input Threshold Voltage | VT+max | | | 2.1 | V | VCC 5.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum Positive-Going Input Threshold Voltage | VT+min | 1.2 | | | V | VCC 4.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum Positive-Going Input Threshold Voltage | VT+min | 1.4 | | | V | VCC 5.5 V; VOUT = 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Maximum Negative-Going Input Threshold Voltage | VT-max | | | 1.2 | V | VCC 4.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Maximum Negative-Going Input Threshold Voltage | VT-max | | | 1.4 | V | VCC 5.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum Negative-Going Input Threshold Voltage | VT-min | 0.5 | | | V | VCC 4.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum Negative-Going Input Threshold Voltage | VT-min | 0.6 | | | V | VCC 5.5 V; VOUT = VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum Hysteresis Voltage | VHmin | 0.4 | | | V | VCC 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | VCC 4.5 V; VIN ≥ VT−min or VT+max; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum High-Level Output Voltage | VOH | 5.4 | | | V | VCC 5.5 V; VIN ≥ VT−min or VT+max; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | VCC 4.5 V; /IOUT/ = 4.0 mA; 125°C | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | VCC 4.5 V; VIN ≥ VT+max; /IOUT/ ≤ 20 µA; 125°C | 4 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | VCC 4.5 V; VIN ≥ VT+max; /IOUT/ = 4.0 mA; 125°C | 4 |
| Maximum Input Leakage Current | IIN | | | 1 | µA | VCC 5.5 V; VIN = VCC or GND; 125°C | 4 |
| Maximum Quiescent Supply Current (per Package) | ICC | | | 40 | µA | VCC 5.5 V; VIN = VCC or GND; IOUT = 0 µA; 125°C | 4 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 38 | ns | VCC 5.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; 125°C | 4 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 22 | ns | VCC 5.0 V; CL = 50 pF; Input tr = tf = 6.0 ns; 125°C | 4 |
| Maximum Input Capacitance | Cin | | | 10 | pF | | 4 |
| Power Dissipation Capacitance (per Gate) | CPD | | 24 | | pF | Typical at 25°C, VCC 5.0 V; Note 8 | 4 |
## CAD (KiCad official)
- Symbol: `MC74HCT132ADR2G`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mc74hct132adr2g-etched.step` / `mc74hct132adr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hct132adr2g.step` / `mc74hct132adr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hct132a-d.pdf) (9 pp, sha256 `e8a59d2445bfc45e`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hct132adr2g-datasheet.pdf)