component

MC74HCT08ADR2G

Public Made by Adom

by adom

onsemi Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icsmc74hct08adr2gfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 20h ago
viewers mc74hct08adr2g: viewers · Ray 20h ago
mc74hct08adr2g-etched.glb Publish 0.1.0 · Ray 20h ago
mc74hct08adr2g-etched.step mc74hct08adr2g: factory component page (tier=mfr) · Ray 20h ago
mc74hct08adr2g-hero.glb mc74hct08adr2g: hero GLB from the etched model (keeps the MPN mark) · Ray 20h ago
mc74hct08adr2g-hero.overlay.json Publish 0.1.0 · Ray 20h ago
mc74hct08adr2g.glb Publish 0.1.0 · Ray 20h ago
mc74hct08adr2g.kicad_mod Publish 0.1.0 · Ray 20h ago
mc74hct08adr2g.kicad_sym Publish 0.1.0 · Ray 20h ago
mc74hct08adr2g.lbr Publish 0.1.0 · Ray 20h ago
mc74hct08adr2g.step Publish 0.1.0 · Ray 20h ago
package.json Publish 0.1.0 · Ray 20h ago
page.json Set visibility: public · Ray 20h ago
README.md Publish 0.1.0 · Ray 20h ago

MC74HCT08ADR2G

onsemi · Gates · SOIC-14

MC74HCT08ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input A1 of AND gate 1; unused inputs must always be tied to GND or VCC.
2 B1 input Input B1 of AND gate 1; unused inputs must always be tied to GND or VCC.
3 Y1 output Output Y1 of AND gate 1 (Y = AB); unused outputs must be left open.
4 A2 input Input A2 of AND gate 2; unused inputs must always be tied to GND or VCC.
5 B2 input Input B2 of AND gate 2; unused inputs must always be tied to GND or VCC.
6 Y2 output Output Y2 of AND gate 2 (Y = AB); unused outputs must be left open.
7 GND power_in Ground reference for all voltages; the datasheet references VCC and all input/output voltages to GND.
8 Y3 output Output Y3 of AND gate 3 (Y = AB); unused outputs must be left open.
9 A3 input Input A3 of AND gate 3; unused inputs must always be tied to GND or VCC.
10 B3 input Input B3 of AND gate 3; unused inputs must always be tied to GND or VCC.
11 Y4 output Output Y4 of AND gate 4 (Y = AB); unused outputs must be left open.
12 A4 input Input A4 of AND gate 4; unused inputs must always be tied to GND or VCC.
13 B4 input Input B4 of AND gate 4; unused inputs must always be tied to GND or VCC.
14 VCC power_in Positive supply pin; the DC supply voltage range is 2.0 V to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 7 V Referenced to GND 2
DC Input Voltage Vin -0.5 V Max is VCC + 0.5 V; referenced to GND 2
DC Output Voltage Vout -0.5 V Max is VCC + 0.5 V; referenced to GND 2
DC Input Current, per Pin Iin -20 20 mA 2
DC Output Current, per Pin Iout -25 25 mA 2
DC Supply Current, VCC and GND Pins ICC -50 50 mA 2
Power Dissipation in Still Air, SOIC Package PD 500 mW Derating -7 mW/°C from 65°C to 125°C 2
Storage Temperature Tstg -65 150 °C 2
Lead Temperature TL 260 °C 1 mm from Case for 10 Seconds, SOIC or TSSOP Package 2
DC Supply Voltage VCC 2 6 V Referenced to GND 2
DC Input Voltage, Output Voltage Vin, Vout 0 V Max is VCC; referenced to GND 2
Operating Temperature, All Package Types TA -55 125 °C 2
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V 2
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V 2
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V 2
Minimum High-Level Input Voltage, -55 to 25°C VIH 2 V Vout = 0.1 V or VCC - 0.1 V, /Iout/ ≤ 20 µA, VCC = 4.5 to 5.5 V 3
Minimum High-Level Input Voltage, ≤85°C VIH 2 V Vout = 0.1 V or VCC - 0.1 V, /Iout/ ≤ 20 µA, VCC = 4.5 to 5.5 V 3
Minimum High-Level Input Voltage, ≤125°C VIH 2 V Vout = 0.1 V or VCC - 0.1 V, /Iout/ ≤ 20 µA, VCC = 4.5 to 5.5 V 3
Maximum Low-Level Input Voltage, -55 to 25°C VIL 0.8 V Vout = 0.1 V or VCC - 0.1 V, /Iout/ ≤ 20 µA, VCC = 4.5 to 5.5 V 3
Maximum Low-Level Input Voltage, ≤85°C VIL 0.8 V Vout = 0.1 V or VCC - 0.1 V, /Iout/ ≤ 20 µA, VCC = 4.5 to 5.5 V 3
Maximum Low-Level Input Voltage, ≤125°C VIL 0.8 V Vout = 0.1 V or VCC - 0.1 V, /Iout/ ≤ 20 µA, VCC = 4.5 to 5.5 V 3
Minimum High-Level Output Voltage, -55 to 25°C VOH 4.4 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 4.5 V 3
Minimum High-Level Output Voltage, -55 to 25°C VOH 5.4 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 5.5 V 3
Minimum High-Level Output Voltage, ≤85°C VOH 4.4 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 4.5 V 3
Minimum High-Level Output Voltage, ≤85°C VOH 5.4 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 5.5 V 3
Minimum High-Level Output Voltage, ≤125°C VOH 4.4 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 4.5 V 3
Minimum High-Level Output Voltage, ≤125°C VOH 5.4 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 5.5 V 3
Minimum High-Level Output Voltage, -55 to 25°C VOH 3.98 V Vin = VIH or VIL, /Iout/ ≤ 4.0 mA, VCC = 4.5 V 3
Minimum High-Level Output Voltage, ≤85°C VOH 3.84 V Vin = VIH or VIL, /Iout/ ≤ 4.0 mA, VCC = 4.5 V 3
Minimum High-Level Output Voltage, ≤125°C VOH 3.7 V Vin = VIH or VIL, /Iout/ ≤ 4.0 mA, VCC = 4.5 V 3
Maximum Low-Level Output Voltage, -55 to 25°C VOL 0.1 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 4.5 V and 5.5 V 3
Maximum Low-Level Output Voltage, ≤85°C VOL 0.1 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 4.5 V and 5.5 V 3
Maximum Low-Level Output Voltage, ≤125°C VOL 0.1 V Vin = VIH or VIL, /Iout/ ≤ 20 µA, VCC = 4.5 V and 5.5 V 3
Maximum Low-Level Output Voltage, -55 to 25°C VOL 0.26 V Vin = VIH or VIL, /Iout/ ≤ 4.0 mA, VCC = 4.5 V 3
Maximum Low-Level Output Voltage, ≤85°C VOL 0.33 V Vin = VIH or VIL, /Iout/ ≤ 4.0 mA, VCC = 4.5 V 3
Maximum Low-Level Output Voltage, ≤125°C VOL 0.4 V Vin = VIH or VIL, /Iout/ ≤ 4.0 mA, VCC = 4.5 V 3
Maximum Input Leakage Current, -55 to 25°C Iin -0.1 0.1 µA Vin = VCC or GND, VCC = 5.5 V 3
Maximum Input Leakage Current, ≤85°C Iin -1 1 µA Vin = VCC or GND, VCC = 5.5 V 3
Maximum Input Leakage Current, ≤125°C Iin -1 1 µA Vin = VCC or GND, VCC = 5.5 V 3
Maximum Quiescent Supply Current (per Package), -55 to 25°C ICC 1 µA Vin = VCC or GND, Iout = 0 µA, VCC = 5.5 V 3
Maximum Quiescent Supply Current (per Package), ≤85°C ICC 10 µA Vin = VCC or GND, Iout = 0 µA, VCC = 5.5 V 3
Maximum Quiescent Supply Current (per Package), ≤125°C ICC 40 µA Vin = VCC or GND, Iout = 0 µA, VCC = 5.5 V 3
Maximum Propagation Delay tPLH, Input A or B to Output Y, -55 to 25°C tPLH 15 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10% 3
Maximum Propagation Delay tPLH, Input A or B to Output Y, ≤85°C tPLH 19 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10% 3
Maximum Propagation Delay tPLH, Input A or B to Output Y, ≤125°C tPLH 22 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10% 3
Maximum Propagation Delay tPHL, Input A or B to Output Y, -55 to 25°C tPHL 17 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10% 3
Maximum Propagation Delay tPHL, Input A or B to Output Y, ≤85°C tPHL 21 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10% 3
Maximum Propagation Delay tPHL, Input A or B to Output Y, ≤125°C tPHL 26 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10% 3
Maximum Output Transition Time, Any Output, -55 to 25°C tTLH, tTHL 15 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V 3
Maximum Output Transition Time, Any Output, ≤85°C tTLH, tTHL 19 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V 3
Maximum Output Transition Time, Any Output, ≤125°C tTLH, tTHL 22 ns CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V 3
Maximum Input Capacitance Cin 10 pF All three temperature columns 3
Power Dissipation Capacitance (Per Buffer) CPD 20 pF Typical @ 25°C, VCC = 5.0 V, VEE = 0 V 3

CAD (KiCad official)

  • Symbol: MC74HCT08ADR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74hct08adr2g-etched.step / mc74hct08adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hct08adr2g.step / mc74hct08adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (6 pp, sha256 deefe3c896d0251c, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF