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MC74HCT04ADTR2G

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onsemi Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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MC74HCT04ADTR2G

onsemi · Logic ICs · TSSOP-14

MC74HCT04ADTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input of inverter 1 (Y1 = A1); TTL/NMOS-compatible input levels, and inputs must be held between GND and VCC with unused inputs tied to GND or VCC.
2 Y1 output Output of inverter 1 (Y = A); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL inputs.
3 A2 input Input of inverter 2 (Y2 = A2); TTL/NMOS-compatible input levels, and inputs must be held between GND and VCC with unused inputs tied to GND or VCC.
4 Y2 output Output of inverter 2 (Y = A); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL inputs.
5 A3 input Input of inverter 3 (Y3 = A3); TTL/NMOS-compatible input levels, and inputs must be held between GND and VCC with unused inputs tied to GND or VCC.
6 Y3 output Output of inverter 3 (Y = A); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL inputs.
7 GND power_in Ground reference for the device (0 V); all voltages are referenced to this pin.
8 Y4 output Output of inverter 4 (Y = A); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL inputs.
9 A4 input Input of inverter 4 (Y4 = A4); TTL/NMOS-compatible input levels, and inputs must be held between GND and VCC with unused inputs tied to GND or VCC.
10 Y5 output Output of inverter 5 (Y = A); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL inputs.
11 A5 input Input of inverter 5 (Y5 = A5); TTL/NMOS-compatible input levels, and inputs must be held between GND and VCC with unused inputs tied to GND or VCC.
12 Y6 output Output of inverter 6 (Y = A); drives 10 LSTTL loads and interfaces directly to CMOS, NMOS and TTL inputs.
13 A6 input Input of inverter 6 (Y6 = A6); TTL/NMOS-compatible input levels, and inputs must be held between GND and VCC with unused inputs tied to GND or VCC.
14 VCC power_in Positive supply; the datasheet specifies 4.5 V to 5.5 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V Referenced to GND 2
DC Input Voltage (Referenced to GND) Vin -0.5 V Referenced to GND; upper limit VCC + 0.5 V 2
DC Output Voltage (Referenced to GND) Vout -0.5 V Referenced to GND; upper limit VCC + 0.5 V 2
DC Input Current, per Pin Iin -20 20 mA Per pin 2
DC Output Current, per Pin Iout -25 25 mA Per pin 2
DC Supply Current, VCC and GND Pins ICC -50 50 mA VCC and GND pins 2
Power Dissipation in Still Air, TSSOP Package PD 450 mW Still air; TSSOP package 2
Storage Temperature Range Tstg -65 150 °C 2
Lead Temperature TL 260 °C 1 mm from case for 10 seconds; SOIC or TSSOP package 2
DC Supply Voltage (Referenced to GND) VCC 4.5 5.5 V Referenced to GND 2
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V Referenced to GND; upper limit VCC 2
Operating Temperature Range, All Package Types TA -55 125 °C All package types 2
Input Rise/Fall Time tr, tf 0 500 ns Figure 1 2
Minimum High-Level Input Voltage VIH 2 V VCC=4.5 V; Vout=0.1 V, /Iout/≤20 µA; −55 to 125 °C 2
Maximum Low-Level Input Voltage VIL 0.8 V VCC=4.5 V; Vout=VCC−0.1 V, /Iout/≤20 µA; −55 to 125 °C 2
Minimum High-Level Output Voltage VOH 4.4 V VCC=4.5 V; Vin=VIL, /Iout/≤20 µA; −55 to 125 °C 2
Minimum High-Level Output Voltage VOH 5.4 V VCC=5.5 V; Vin=VIL, /Iout/≤20 µA; −55 to 125 °C 2
Minimum High-Level Output Voltage VOH 3.98 V VCC=4.5 V; Vin=VIL, /Iout/≤4.0 mA; −55 to 25 °C 2
Minimum High-Level Output Voltage VOH 3.84 V VCC=4.5 V; Vin=VIL, /Iout/≤4.0 mA; ≤85 °C 2
Minimum High-Level Output Voltage VOH 3.7 V VCC=4.5 V; Vin=VIL, /Iout/≤4.0 mA; ≤125 °C 2
Maximum Low-Level Output Voltage VOL 0.1 V VCC=4.5 V; Vin=VIH, /Iout/≤20 µA; −55 to 125 °C 2
Maximum Low-Level Output Voltage VOL 0.26 V VCC=4.5 V; Vin=VIH, /Iout/≤4.0 mA; −55 to 25 °C 2
Maximum Low-Level Output Voltage VOL 0.33 V VCC=4.5 V; Vin=VIH, /Iout/≤4.0 mA; ≤85 °C 2
Maximum Low-Level Output Voltage VOL 0.4 V VCC=4.5 V; Vin=VIH, /Iout/≤4.0 mA; ≤125 °C 2
Maximum Input Leakage Current Iin -0.1 0.1 µA VCC=5.5 V; Vin=VCC or GND; −55 to 25 °C 2
Maximum Input Leakage Current Iin -1 1 µA VCC=5.5 V; Vin=VCC or GND; ≤85 °C 2
Maximum Quiescent Supply Current (per Package) ICC 1 µA VCC=5.5 V; Vin=VCC or GND; Iout=0A; −55 to 25 °C 2
Maximum Quiescent Supply Current (per Package) ICC 10 µA VCC=5.5 V; Vin=VCC or GND; Iout=0A; ≤85 °C 2
Maximum Quiescent Supply Current (per Package) ICC 40 µA VCC=5.5 V; Vin=VCC or GND; Iout=0A; ≤125 °C 2
Additional Quiescent Supply Current ICC 2.9 mA VCC=5.5 V; Vin=2.4 V any one input; other inputs VCC or GND; Iout=0A; −55 °C column 2
Additional Quiescent Supply Current ICC 2.4 mA VCC=5.5 V; Vin=2.4 V any one input; other inputs VCC or GND; Iout=0A; 25 to 125 °C column 2
Maximum Propagation Delay, Input A to Output Y tPLH 15 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; −55 to 25 °C 3
Maximum Propagation Delay, Input A to Output Y tPLH 19 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; ≤85 °C 3
Maximum Propagation Delay, Input A to Output Y tPLH 22 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; ≤125 °C 3
Maximum Propagation Delay, Input A to Output Y tPHL 17 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; −55 to 25 °C 3
Maximum Propagation Delay, Input A to Output Y tPHL 21 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; ≤85 °C 3
Maximum Propagation Delay, Input A to Output Y tPHL 26 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; ≤125 °C 3
Maximum Output Transition Time, Any Output tTLH, tTHL 15 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; −55 to 25 °C; Figures 1 and 2 3
Maximum Output Transition Time, Any Output tTLH, tTHL 19 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; ≤85 °C; Figures 1 and 2 3
Maximum Output Transition Time, Any Output tTLH, tTHL 22 ns VCC=5.0 V ±10%, CL=50 pF, tr=tf=6 ns; ≤125 °C; Figures 1 and 2 3
Maximum Input Capacitance Cin 10 pF 3

CAD (KiCad official)

  • Symbol: MC74HCT04ADTR2G
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: mc74hct04adtr2g-etched.step / mc74hct04adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hct04adtr2g.step / mc74hct04adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (5 pp, sha256 4f4ef6fa343cb5ca, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF