component
MC74HC86ADG
Public Made by Adomby adom
onsemi Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
MC74HC86ADG
onsemi · Logic Gates · SOIC-14
MC74HC86ADG from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Data input A of gate 1 (Y1 = A1 ⊕ B1); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 2 | B1 | input | Data input B of gate 1 (Y1 = A1 ⊕ B1); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 3 | Y1 | output | Output of gate 1 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 4 | A2 | input | Data input A of gate 2 (Y2 = A2 ⊕ B2); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 5 | B2 | input | Data input B of gate 2 (Y2 = A2 ⊕ B2); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 6 | Y2 | output | Output of gate 2 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 7 | GND | power_in | Ground reference for the device; all DC supply, input and output voltages are referenced to GND. |
| 8 | Y3 | output | Output of gate 3 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 9 | A3 | input | Data input A of gate 3 (Y3 = A3 ⊕ B3); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 10 | B3 | input | Data input B of gate 3 (Y3 = A3 ⊕ B3); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 11 | Y4 | output | Output of gate 4 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 12 | A4 | input | Data input A of gate 4 (Y4 = A4 ⊕ B4); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 13 | B4 | input | Data input B of gate 4 (Y4 = A4 ⊕ B4); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply; recommended DC supply voltage is 2.0 V to 6.0 V referenced to GND, with an absolute maximum of −0.5 to +7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (recommended operating) | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input Voltage, Output Voltage (recommended operating) | Vin, Vout | 0 | V | Referenced to GND; upper limit printed as VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | All package types | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V; Figure 1 | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V; Figure 1 | 2 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V; Figure 1 | 2 | |
| DC Supply Voltage (absolute maximum) | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage (absolute maximum) | Vin | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 2 | ||
| DC Output Voltage (absolute maximum) | Vout | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | Per pin | 2 | |
| DC Output Current, per Pin | Iout | -25 | 25 | mA | Per pin | 2 | |
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | VCC and GND pins | 2 | |
| Power Dissipation in Still Air | PD | 500 | mW | SOIC package | 2 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds (plastic DIP, SOIC or TSSOP package) | 2 | ||
| Minimum High-Level Input Voltage | VIH | 1.5 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V; limit identical in all temperature columns | 2 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V; limit identical in all temperature columns | 2 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V; limit identical in all temperature columns | 2 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V; limit identical in all temperature columns | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V; limit identical in all temperature columns | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V; limit identical in all temperature columns | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V; limit identical in all temperature columns | 2 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V; limit identical in all temperature columns | 2 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V | 2 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 4.5 V | 2 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 6.0 V | 2 | ||
| Minimum High-Level Output Voltage | VOH | 2.2 | V | Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V; 125 °C column | 2 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC = 4.5 V; 125 °C column | 2 | ||
| Minimum High-Level Output Voltage | VOH | 5.2 | V | Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; VCC = 6.0 V; 125 °C column | 2 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V | 2 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V; 125 °C column | 2 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | Vin = VCC or GND; VCC = 6.0 V; 125 °C column | 2 | |
| Maximum Quiescent Supply Current (per package) | ICC | 40 | µA | Vin = VCC or GND; Iout = 0 µA; VCC = 6.0 V; 125 °C column | 2 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 150 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 2.0 V; 125 °C column | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 110 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 3.0 V; 125 °C column | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 31 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 4.5 V; 125 °C column | 3 | ||
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | 26 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 6.0 V; 125 °C column | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 110 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 2.0 V; 125 °C column | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 55 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 3.0 V; 125 °C column | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 22 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 4.5 V; 125 °C column | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 19 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 6.0 V; 125 °C column | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 3 | |||
| Power Dissipation Capacitance (per gate) | CPD | 33 | pF | Typical at 25 °C, VCC = 5.0 V; per gate | 3 |
CAD (KiCad official)
- Symbol:
MC74HC86ADG - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
mc74hc86adg-etched.step/mc74hc86adg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc86adg.step/mc74hc86adg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (8 pp, sha256
d1826447ffc08617, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MC74HC86ADG
**onsemi** · Logic Gates · SOIC-14
MC74HC86ADG from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Data input A of gate 1 (Y1 = A1 ⊕ B1); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 2 | B1 | input | Data input B of gate 1 (Y1 = A1 ⊕ B1); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 3 | Y1 | output | Output of gate 1 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 4 | A2 | input | Data input A of gate 2 (Y2 = A2 ⊕ B2); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 5 | B2 | input | Data input B of gate 2 (Y2 = A2 ⊕ B2); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 6 | Y2 | output | Output of gate 2 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 7 | GND | power_in | Ground reference for the device; all DC supply, input and output voltages are referenced to GND. |
| 8 | Y3 | output | Output of gate 3 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 9 | A3 | input | Data input A of gate 3 (Y3 = A3 ⊕ B3); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 10 | B3 | input | Data input B of gate 3 (Y3 = A3 ⊕ B3); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 11 | Y4 | output | Output of gate 4 (Y = A ⊕ B); DC output current is limited to ±25 mA per pin, and unused outputs must be left open. |
| 12 | A4 | input | Data input A of gate 4 (Y4 = A4 ⊕ B4); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 13 | B4 | input | Data input B of gate 4 (Y4 = A4 ⊕ B4); Vin must be constrained to the range GND to VCC, and unused inputs must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply; recommended DC supply voltage is 2.0 V to 6.0 V referenced to GND, with an absolute maximum of −0.5 to +7.0 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (recommended operating) | VCC | 2 | | 6 | V | Referenced to GND | 2 |
| DC Input Voltage, Output Voltage (recommended operating) | Vin, Vout | 0 | | | V | Referenced to GND; upper limit printed as VCC | 2 |
| Operating Temperature, All Package Types | TA | -55 | | 125 | °C | All package types | 2 |
| Input Rise and Fall Time | tr, tf | 0 | | 1000 | ns | VCC = 2.0 V; Figure 1 | 2 |
| Input Rise and Fall Time | tr, tf | 0 | | 500 | ns | VCC = 4.5 V; Figure 1 | 2 |
| Input Rise and Fall Time | tr, tf | 0 | | 400 | ns | VCC = 6.0 V; Figure 1 | 2 |
| DC Supply Voltage (absolute maximum) | VCC | -0.5 | | 7 | V | Referenced to GND | 2 |
| DC Input Voltage (absolute maximum) | Vin | -0.5 | | | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 2 |
| DC Output Voltage (absolute maximum) | Vout | -0.5 | | | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 2 |
| DC Input Current, per Pin | Iin | -20 | | 20 | mA | Per pin | 2 |
| DC Output Current, per Pin | Iout | -25 | | 25 | mA | Per pin | 2 |
| DC Supply Current, VCC and GND Pins | ICC | -50 | | 50 | mA | VCC and GND pins | 2 |
| Power Dissipation in Still Air | PD | | | 500 | mW | SOIC package | 2 |
| Storage Temperature | Tstg | -65 | | 150 | °C | | 2 |
| Lead Temperature | TL | | | 260 | °C | 1 mm from case for 10 seconds (plastic DIP, SOIC or TSSOP package) | 2 |
| Minimum High-Level Input Voltage | VIH | 1.5 | | | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V; limit identical in all temperature columns | 2 |
| Minimum High-Level Input Voltage | VIH | 2.1 | | | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V; limit identical in all temperature columns | 2 |
| Minimum High-Level Input Voltage | VIH | 3.15 | | | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V; limit identical in all temperature columns | 2 |
| Minimum High-Level Input Voltage | VIH | 4.2 | | | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V; limit identical in all temperature columns | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 0.5 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V; limit identical in all temperature columns | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 0.9 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V; limit identical in all temperature columns | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 1.35 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V; limit identical in all temperature columns | 2 |
| Maximum Low-Level Input Voltage | VIL | | | 1.8 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V; limit identical in all temperature columns | 2 |
| Minimum High-Level Output Voltage | VOH | 1.9 | | | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V | 2 |
| Minimum High-Level Output Voltage | VOH | 4.4 | | | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 4.5 V | 2 |
| Minimum High-Level Output Voltage | VOH | 5.9 | | | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 6.0 V | 2 |
| Minimum High-Level Output Voltage | VOH | 2.2 | | | V | Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V; 125 °C column | 2 |
| Minimum High-Level Output Voltage | VOH | 3.7 | | | V | Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC = 4.5 V; 125 °C column | 2 |
| Minimum High-Level Output Voltage | VOH | 5.2 | | | V | Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; VCC = 6.0 V; 125 °C column | 2 |
| Maximum Low-Level Output Voltage | VOL | | | 0.1 | V | Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V | 2 |
| Maximum Low-Level Output Voltage | VOL | | | 0.4 | V | Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V; 125 °C column | 2 |
| Maximum Input Leakage Current | Iin | -1 | | 1 | µA | Vin = VCC or GND; VCC = 6.0 V; 125 °C column | 2 |
| Maximum Quiescent Supply Current (per package) | ICC | | | 40 | µA | Vin = VCC or GND; Iout = 0 µA; VCC = 6.0 V; 125 °C column | 2 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 150 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 2.0 V; 125 °C column | 3 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 110 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 3.0 V; 125 °C column | 3 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 31 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 4.5 V; 125 °C column | 3 |
| Maximum Propagation Delay, Input A or B to Output Y | tPLH, tPHL | | | 26 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 6.0 V; 125 °C column | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 110 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 2.0 V; 125 °C column | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 55 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 3.0 V; 125 °C column | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 22 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 4.5 V; 125 °C column | 3 |
| Maximum Output Transition Time, Any Output | tTLH, tTHL | | | 19 | ns | CL = 50 pF; tr = tf = 6 ns; VCC = 6.0 V; 125 °C column | 3 |
| Maximum Input Capacitance | Cin | | | 10 | pF | | 3 |
| Power Dissipation Capacitance (per gate) | CPD | | 33 | | pF | Typical at 25 °C, VCC = 5.0 V; per gate | 3 |
## CAD (KiCad official)
- Symbol: `MC74HC86ADG`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `mc74hc86adg-etched.step` / `mc74hc86adg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc86adg.step` / `mc74hc86adg.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929471080501248) (8 pp, sha256 `d1826447ffc08617`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mc74hc86adg-datasheet.pdf)