component
MC74HC597ADR2G
Public Made by Adomby adom
onsemi Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC597ADR2G
onsemi · Shift Registers · SOIC-16
MC74HC597ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Parallel data input B, stored in the input latch on the rising edge of Latch Clock. |
| 2 | C | input | Parallel data input C, stored in the input latch on the rising edge of Latch Clock. |
| 3 | D | input | Parallel data input D, stored in the input latch on the rising edge of Latch Clock. |
| 4 | E | input | Parallel data input E, stored in the input latch on the rising edge of Latch Clock. |
| 5 | F | input | Parallel data input F, stored in the input latch on the rising edge of Latch Clock. |
| 6 | G | input | Parallel data input G, stored in the input latch on the rising edge of Latch Clock. |
| 7 | H | input | Parallel data input H, stored in the input latch on the rising edge of Latch Clock. |
| 8 | GND | power_in | Ground reference for the device; all voltages are referenced to GND, and Vin and Vout must stay between GND and VCC. |
| 9 | QH | output | Serial data output from the last stage of the shift register. |
| 10 | Reset | input | Asynchronous active-low shift register reset that clears the shift register to low without changing the input latch contents. |
| 11 | Shift Clock | input | Serial shift register clock; a low-to-high transition shifts serial data in at SA and shifts stage H out to QH. |
| 12 | Latch Clock | input | A low-to-high transition on this input loads parallel data inputs A-H into the input latch. |
| 13 | Serial Shift/Parallel Load | input | A high level allows the shift register to shift serially, while a low level loads parallel data from the input latch and inhibits serial shifting. |
| 14 | SA | input | Serial data input shifted into the shift register on the rising Shift Clock edge when Serial Shift/Parallel Load is high, and ignored when it is low. |
| 15 | A | input | Parallel data input A, stored in the input latch on the rising edge of Latch Clock. |
| 16 | VCC | power_in | Positive supply; recommended DC supply voltage is 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Referenced to GND; upper limit printed as VCC + 0.5 V | 3 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | per pin | 3 | |
| DC Output Current, per Pin | Iout | -25 | 25 | mA | per pin | 3 | |
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | VCC and GND pins | 3 | |
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | SOIC package; derate 7 mW/C from 65 to 125 C | 3 | ||
| Storage Temperature | Tstg | -65 | 150 | C | 3 | ||
| Lead Temperature, 1 mm from Case for 10 Seconds | TL | 260 | C | Plastic DIP, SOIC or TSSOP package | 3 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | Referenced to GND | 3 | |
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Referenced to GND; upper limit printed as VCC | 3 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | C | 3 | ||
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 600 | ns | VCC = 3.0 V (Figure 1) | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 3 | |
| Minimum High-Level Input Voltage | VIH | 1.5 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 2.0 V | 4 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 3.0 V | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 4.5 V | 4 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 6.0 V | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 2.0 V | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 3.0 V | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 4.5 V | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 μA; VCC = 6.0 V | 4 | ||
| Minimum High-Level Output Voltage | VOH | 1.9 | V | Vin = VIH or VIL; /Iout/ ≤ 20 μA; VCC = 2.0 V | 4 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | Vin = VIH or VIL; /Iout/ ≤ 20 μA; VCC = 4.5 V | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.9 | V | Vin = VIH or VIL; /Iout/ ≤ 20 μA; VCC = 6.0 V | 4 | ||
| Minimum High-Level Output Voltage | VOH | 2.2 | V | Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V | 4 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC = 4.5 V | 4 | ||
| Minimum High-Level Output Voltage | VOH | 5.2 | V | Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; VCC = 6.0 V | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | Vin = VIH or VIL; /Iout/ ≤ 20 μA; VCC = 2.0 V | 4 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V | 4 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | μA | Vin = VCC or GND; VCC = 6.0 V | 4 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | μA | Vin = VCC or GND; Iout = 0 μA; VCC = 6.0 V | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle), Shift Clock | fmax | 8 | MHz | CL = 50 pF; input tr = tf = 6 ns; VCC = 2.0 V | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle), Shift Clock | fmax | 12 | MHz | CL = 50 pF; input tr = tf = 6 ns; VCC = 3.0 V | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle), Shift Clock | fmax | 25 | MHz | CL = 50 pF; input tr = tf = 6 ns; VCC = 4.5 V | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle), Shift Clock | fmax | 40 | MHz | CL = 50 pF; input tr = tf = 6 ns; VCC = 6.0 V | 5 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 5 | |||
| Maximum Propagation Delay, Latch Clock to QH | tPLH, tPHL | 275 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 2.0 V | 5 | ||
| Maximum Propagation Delay, Latch Clock to QH | tPLH, tPHL | 125 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 3.0 V | 5 | ||
| Maximum Propagation Delay, Latch Clock to QH | tPLH, tPHL | 60 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 4.5 V | 5 | ||
| Maximum Propagation Delay, Latch Clock to QH | tPLH, tPHL | 50 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 6.0 V | 5 | ||
| Maximum Propagation Delay, Shift Clock to QH | tPLH, tPHL | 240 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 2.0 V | 5 | ||
| Maximum Propagation Delay, Shift Clock to QH | tPLH, tPHL | 160 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 3.0 V | 5 | ||
| Maximum Propagation Delay, Shift Clock to QH | tPLH, tPHL | 48 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 4.5 V | 5 | ||
| Maximum Propagation Delay, Shift Clock to QH | tPLH, tPHL | 40 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 6.0 V | 5 | ||
| Maximum Propagation Delay, Reset to QH | tPHL | 240 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 2.0 V | 5 | ||
| Maximum Propagation Delay, Reset to QH | tPHL | 160 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 3.0 V | 5 | ||
| Maximum Propagation Delay, Reset to QH | tPHL | 48 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 4.5 V | 5 | ||
| Maximum Propagation Delay, Reset to QH | tPHL | 40 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 6.0 V | 5 | ||
| Maximum Propagation Delay, Serial Shift/Parallel Load to QH | tPLH, tPHL | 240 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 2.0 V | 5 | ||
| Maximum Propagation Delay, Serial Shift/Parallel Load to QH | tPLH, tPHL | 160 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 3.0 V | 5 | ||
| Maximum Propagation Delay, Serial Shift/Parallel Load to QH | tPLH, tPHL | 48 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 4.5 V | 5 | ||
| Maximum Propagation Delay, Serial Shift/Parallel Load to QH | tPLH, tPHL | 40 | ns | CL = 50 pF; input tr = tf = 6 ns; VCC = 6.0 V | 5 |
CAD (KiCad official)
- Symbol:
MC74HC597ADR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc597adr2g-etched.step/mc74hc597adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc597adr2g.step/mc74hc597adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (12 pp, sha256
01e622c0077f8ec4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).