MC74HC595ADTR2G

{
  "schema_version": 1,
  "type": "component",
  "slug": "mc74hc595adtr2g",
  "title": "MC74HC595ADTR2G",
  "brief": "onsemi Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "logic",
    "mc74hc595adtr2g"
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  "component": {
    "mpn": "MC74HC595ADTR2G",
    "manufacturer": "onsemi",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://www.onsemi.com/pdf/datasheet/mc74hc595adtr2-d.pdf",
    "parts": {
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      "footprint": "mc74hc595adtr2g.kicad_mod",
      "model_3d": "mc74hc595adtr2g-etched.glb",
      "model_3d_plain": "mc74hc595adtr2g.glb",
      "model_3d_step": "mc74hc595adtr2g-etched.step",
      "model_3d_step_plain": "mc74hc595adtr2g.step",
      "lbr": "mc74hc595adtr2g.lbr"
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    "distributor_links": {
      "lcsc": "C100027"
    },
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Parallel data output bit B from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE (pin 13) is LOW; drives up to 15 LSTTL loads. Output goes to high-impedance when OE is HIGH."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Parallel data output bit C from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Parallel data output bit D from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Parallel data output bit E from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Parallel data output bit F from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Parallel data output bit G from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Parallel data output bit H (MSB position) from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Common return for supply and I/O."
      },
      {
        "number": "9",
        "name": "SQH",
        "type": "output",
        "description": "Serial data output from the shift register (Q_H of the shift stage, not the latch). Used to cascade multiple MC74HC595A devices; connects to the A (serial data input) of the next stage. Not affected by OUTPUT ENABLE."
      },
      {
        "number": "10",
        "name": "RESET",
        "type": "input",
        "description": "Asynchronous active-LOW reset for the shift register only. When LOW, all shift-register stages are cleared to 0; the storage latch is not affected until a LATCH CLOCK edge propagates the cleared data."
      },
      {
        "number": "11",
        "name": "SHIFT_CLOCK",
        "type": "input",
        "description": "Shift-register clock input (SPI SCK equivalent). On the LOW-to-HIGH transition, serial data on A (pin 14) is clocked into stage QA and the shift register advances one bit toward SQH. f_max = 24-35 MHz at Vcc = 6 V."
      },
      {
        "number": "12",
        "name": "LATCH_CLOCK",
        "type": "input",
        "description": "Storage latch (register) clock. On the LOW-to-HIGH transition, the current shift-register contents are transferred into the 8-bit output latch driving QA-QH. Typically the SPI /CS or 'RCLK' line."
      },
      {
        "number": "13",
        "name": "OUTPUT_ENABLE",
        "type": "input",
        "description": "Active-LOW output enable for the parallel outputs QA-QH. LOW enables the 3-state drivers; HIGH forces QA-QH into high-impedance. Does not affect the shift register, latch contents, or SQH."
      },
      {
        "number": "14",
        "name": "A",
        "type": "input",
        "description": "Serial data input to the shift register (SPI MOSI equivalent). Sampled on the rising edge of SHIFT CLOCK and loaded into stage QA."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Parallel data output bit A (LSB position) from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply rail. Recommended operating range 2.0 V to 6.0 V (absolute max 7.0 V). Bypass with 0.1 uF close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.onsemi.com/pdf/datasheet/mc74hc595adtr2-d.pdf",
        "pages": 13,
        "sha256": "77ce5ff50b90c4e5",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.8625,
        -2.275
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC595",
      "logic_family": "74HC",
      "function_code": "595",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit SIPO Shift Register with Output Latch",
      "manufacturer": "Onsemi (Motorola legacy)",
      "is_specialty": false
    }
  },
  "metadata": {
    "specs": {
      "Manufacturer": "onsemi",
      "Package": "TSSOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
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    "info"
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  "discovery_triggers": [
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  "discovery_pitch": "MC74HC595ADTR2G (onsemi) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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  "files": [
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  "visibility": {
    "public": true
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  "variants": [
    {
      "mpn": "MC74HC595ADTR2G",
      "kind": "packaging"
    },
    {
      "mpn": "MC74HC595ADTR2GDR2G",
      "kind": "packaging"
    },
    {
      "mpn": "MC74HC595ADTR2GDG",
      "kind": "packaging"
    },
    {
      "mpn": "MC74HC595ADTR2GMNR4G",
      "kind": "packaging"
    },
    {
      "mpn": "MC74HC595ADTR2GMN",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-28T18:53:18.142Z"
}