MC74HC595ADTR2G

{
 "schema": "adom.pads/1",
 "slug": "mc74hc595adtr2g",
 "footprint": "TSSOP-16_4.4x5mm_P0.65mm",
 "generated_from": {
  "footprint": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -2.8625,
   -2.275
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754"
 },
 "pad_count": 16,
 "symbol_pins": [
  "1",
  "10",
  "11",
  "12",
  "13",
  "14",
  "15",
  "16",
  "2",
  "3",
  "4",
  "5",
  "6",
  "7",
  "8",
  "9"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    -2.275
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "QB",
   "type": "tri_state",
   "description": "Parallel data output bit B from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE (pin 13) is LOW; drives up to 15 LSTTL loads. Output goes to high-impedance when OE is HIGH.",
   "is_pin1": true,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    -1.625
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "QC",
   "type": "tri_state",
   "description": "Parallel data output bit C from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    -0.975
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "QD",
   "type": "tri_state",
   "description": "Parallel data output bit D from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    -0.325
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "QE",
   "type": "tri_state",
   "description": "Parallel data output bit E from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    0.325
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "QF",
   "type": "tri_state",
   "description": "Parallel data output bit F from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    0.975
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "QG",
   "type": "tri_state",
   "description": "Parallel data output bit G from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "7",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    1.625
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "7",
   "name": "QH",
   "type": "tri_state",
   "description": "Parallel data output bit H (MSB position) from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "8",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.8625,
    2.275
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "8",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference (0 V). Common return for supply and I/O.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "9",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    2.275
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "9",
   "name": "SQH",
   "type": "output",
   "description": "Serial data output from the shift register (Q_H of the shift stage, not the latch). Used to cascade multiple MC74HC595A devices; connects to the A (serial data input) of the next stage. Not affected by OUTPUT ENABLE.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "10",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    1.625
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "10",
   "name": "RESET",
   "type": "input",
   "description": "Asynchronous active-LOW reset for the shift register only. When LOW, all shift-register stages are cleared to 0; the storage latch is not affected until a LATCH CLOCK edge propagates the cleared data.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "11",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    0.975
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "11",
   "name": "SHIFT_CLOCK",
   "type": "input",
   "description": "Shift-register clock input (SPI SCK equivalent). On the LOW-to-HIGH transition, serial data on A (pin 14) is clocked into stage QA and the shift register advances one bit toward SQH. f_max = 24-35 MHz at Vcc = 6 V.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "12",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    0.325
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "12",
   "name": "LATCH_CLOCK",
   "type": "input",
   "description": "Storage latch (register) clock. On the LOW-to-HIGH transition, the current shift-register contents are transferred into the 8-bit output latch driving QA-QH. Typically the SPI /CS or 'RCLK' line.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "13",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    -0.325
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "13",
   "name": "OUTPUT_ENABLE",
   "type": "input",
   "description": "Active-LOW output enable for the parallel outputs QA-QH. LOW enables the 3-state drivers; HIGH forces QA-QH into high-impedance. Does not affect the shift register, latch contents, or SQH.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "14",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    -0.975
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "14",
   "name": "A",
   "type": "input",
   "description": "Serial data input to the shift register (SPI MOSI equivalent). Sampled on the rising edge of SHIFT CLOCK and loaded into stage QA.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "15",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    -1.625
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "15",
   "name": "QA",
   "type": "tri_state",
   "description": "Parallel data output bit A (LSB position) from the storage latch. 3-state CMOS output, enabled when OUTPUT ENABLE is LOW.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "16",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.8625,
    -2.275
   ],
   "rot": 0.0,
   "size": [
    1.475,
    0.4
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "16",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply rail. Recommended operating range 2.0 V to 6.0 V (absolute max 7.0 V). Bypass with 0.1 uF close to the pin.",
   "is_pin1": false,
   "source": {
    "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}