component
MC74HC595ADTG
Public Made by Adomby adom
onsemi Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74HC595ADTG
onsemi · Shift Registers · TSSOP-16
MC74HC595ADTG from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 2 | QC | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 3 | QD | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 4 | QE | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 5 | QF | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 6 | QG | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 7 | QH | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 8 | GND | power_in | Ground reference; all input, output and supply voltages are referenced to this pin. |
| 9 | SQH | output | Noninverted serial data output from the eighth shift-register stage; it does not have three-state capability. |
| 10 | RESET | input | Active-low, asynchronous reset of the shift register only; a low resets the shift register and does not affect the 8-bit latch. |
| 11 | SHIFT CLOCK | input | Shift register clock; a low-to-high transition shifts the data at the Serial Input A into the 8-bit shift register. |
| 12 | LATCH CLOCK | input | Storage latch clock; a low-to-high transition latches the shift register data into the output latch. |
| 13 | OUTPUT ENABLE | input | Active-low output enable; a low presents the latch data at QA-QH, a high forces QA-QH into high impedance, and the serial output is unaffected. |
| 14 | A | input | Serial data input that is shifted into the 8-bit serial shift register. |
| 15 | QA | tri_state | Noninverted, 3-state parallel latch output, forced to high impedance when Output Enable is high. |
| 16 | VCC | power_in | Positive supply, specified from 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | 3 | ||
| DC Input Voltage, Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Upper limit printed as VCC | 3 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | All package types | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V (Figure 1) | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 500 | ns | VCC = 4.5 V (Figure 1) | 3 | |
| Input Rise and Fall Time | tr, tf | 0 | 400 | ns | VCC = 6.0 V (Figure 1) | 3 | |
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | Referenced to GND | 3 | |
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Referenced to GND; upper limit printed as VCC+0.5 | 3 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Referenced to GND; upper limit printed as VCC+0.5 | 3 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | Per pin | 3 | |
| DC Output Current, per Pin | Iout | -35 | 35 | mA | Per pin | 3 | |
| DC Supply Current, VCC and GND Pins | ICC | -75 | 75 | mA | VCC and GND pins | 3 | |
| Power Dissipation in Still Air, TSSOP Package | PD | 450 | mW | Still air, TSSOP package | 3 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead Temperature, 1 mm from Case for 10 Seconds | TL | 260 | °C | 1 mm from case for 10 s; plastic DIP, SOIC or TSSOP package | 3 | ||
| ESD Withstand Voltage, Human Body Model | VESD | 3000 | V | Human body model, EIA/JESD22-A114-A; printed as >3000 | 3 | ||
| Minimum High-Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum High-Level Input Voltage | VIH | 2.1 | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum High-Level Input Voltage | VIH | 3.15 | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum High-Level Input Voltage | VIH | 4.2 | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 0.9 | V | VCC = 3.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.35 | V | VCC = 4.5 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Maximum Low-Level Input Voltage | VIL | 1.8 | V | VCC = 6.0 V; Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA | 4 | ||
| Minimum High-Level Output Voltage, QA-QH | VOH | 2.2 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 4 | ||
| Minimum High-Level Output Voltage, QA-QH | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 6.0 mA | 4 | ||
| Minimum High-Level Output Voltage, QA-QH | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 7.8 mA | 4 | ||
| Maximum Low-Level Output Voltage, QA-QH | VOL | 0.4 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 2.2 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 3.7 | V | VCC = 4.5 V; Vin = VIH or VIL; /Iout/ ≤ 4.0 mA | 4 | ||
| Minimum High-Level Output Voltage, SQH | VOH | 5.2 | V | VCC = 6.0 V; Vin = VIH or VIL; /Iout/ ≤ 5.2 mA | 4 | ||
| Maximum Low-Level Output Voltage, SQH | VOL | 0.4 | V | VCC = 3.0 V; Vin = VIH or VIL; /Iout/ ≤ 2.4 mA | 4 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC = 6.0 V; Vin = VCC or GND | 4 | |
| Maximum Three-State Leakage Current, QA-QH | IOZ | -10 | 10 | µA | VCC = 6.0 V; output high-impedance; Vin = VIL or VIH; Vout = VCC or GND | 4 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 160 | µA | VCC = 6.0 V; Vin = VCC or GND; Iout = 0 µA | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 4 | MHz | VCC = 2.0 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 8 | MHz | VCC = 3.0 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 20 | MHz | VCC = 4.5 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 24 | MHz | VCC = 6.0 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL | 210 | ns | VCC = 2.0 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL | 150 | ns | VCC = 3.0 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL | 42 | ns | VCC = 4.5 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Propagation Delay, Shift Clock to SQH | tPLH, tPHL | 36 | ns | VCC = 6.0 V; CL = 50 pF (Figures 1 and 7) | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL | 210 | ns | VCC = 2.0 V; CL = 50 pF (Figures 3 and 7) | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL | 150 | ns | VCC = 3.0 V; CL = 50 pF (Figures 3 and 7) | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL | 42 | ns | VCC = 4.5 V; CL = 50 pF (Figures 3 and 7) | 5 | ||
| Maximum Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL | 36 | ns | VCC = 6.0 V; CL = 50 pF (Figures 3 and 7) | 5 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 75 | ns | VCC = 2.0 V (Figure 5) | 6 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 60 | ns | VCC = 3.0 V (Figure 5) | 6 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 15 | ns | VCC = 4.5 V (Figure 5) | 6 | ||
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu | 13 | ns | VCC = 6.0 V (Figure 5) | 6 | ||
| Minimum Hold Time, Shift Clock to Serial Data Input A | th | 5 | ns | VCC = 2.0 V (Figure 5) | 6 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 5 |
CAD (KiCad official)
- Symbol:
MC74HC595ADTG - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc595adtg-etched.step/mc74hc595adtg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc595adtg.step/mc74hc595adtg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (14 pp, sha256
d99b368a96a26071, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).