# MC74HC595ADG

**onsemi** · Registers · SOIC-16

MC74HC595ADG from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Noninverted, 3-state latch output B, placed in high impedance when Output Enable is high. |
| 2 | QC | tri_state | Noninverted, 3-state latch output C, placed in high impedance when Output Enable is high. |
| 3 | QD | tri_state | Noninverted, 3-state latch output D, placed in high impedance when Output Enable is high. |
| 4 | QE | tri_state | Noninverted, 3-state latch output E, placed in high impedance when Output Enable is high. |
| 5 | QF | tri_state | Noninverted, 3-state latch output F, placed in high impedance when Output Enable is high. |
| 6 | QG | tri_state | Noninverted, 3-state latch output G, placed in high impedance when Output Enable is high. |
| 7 | QH | tri_state | Noninverted, 3-state latch output H, placed in high impedance when Output Enable is high. |
| 8 | GND | power_in | Ground pin (GND = pin 8). |
| 9 | SQH | output | Noninverted serial data output from the eighth stage of the shift register; it does not have three-state capability. |
| 10 | RESET | input | Active-low asynchronous reset input that resets the shift register only; the 8-bit latch is not affected. |
| 11 | SHIFT CLOCK | input | Shift register clock input; a low-to-high transition shifts the data at serial input A into the 8-bit shift register. |
| 12 | LATCH CLOCK | input | Storage latch clock input; a low-to-high transition latches the shift register data. |
| 13 | OUTPUT ENABLE | input | Active-low output enable; low presents latch data at the outputs, high forces QA-QH into high impedance and does not affect the serial output. |
| 14 | A | input | Serial data input whose data is shifted into the 8-bit serial shift register. |
| 15 | QA | tri_state | Noninverted, 3-state latch output A, placed in high impedance when Output Enable is high. |
| 16 | VCC | power_in | Positive supply (VCC = pin 16); 2.0 to 6.0 V for MC74HC595A, absolute maximum -0.5 to +6.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic ICs |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 |  | 6.5 | V |  | 3 |
| DC Input Voltage | VIN | -0.5 |  |  | V | -0.5 to VCC + 0.5 | 3 |
| DC Output Voltage | VOUT | -0.5 |  |  | V | -0.5 to VCC + 0.5 | 3 |
| DC Input Current, per Pin | IIN | -20 |  | 20 | mA |  | 3 |
| DC Output Current, per Pin | IOUT | -35 |  | 35 | mA |  | 3 |
| DC Supply Current, VCC and GND Pins | ICC | -75 |  | 75 | mA |  | 3 |
| Input Clamp Current | IIK | -20 |  | 20 | mA | VIN < 0 or VIN > VCC | 3 |
| Output Clamp Current | IOK | -20 |  | 20 | mA | VOUT < 0 or VOUT > VCC | 3 |
| Storage Temperature | TSTG | -65 |  | 150 | °C |  | 3 |
| Lead Temperature | TL |  |  | 260 | °C | 1 mm from case for 10 seconds | 3 |
| Junction Temperature Under Bias | TJ | -150 |  | 150 | °C |  | 3 |
| ESD Withstand Voltage, HBM | VESD | 3000 |  |  | V | Human Body Model, >3000 | 3 |
| ESD Withstand Voltage, CDM | VESD | 1000 |  |  | V | Charged Device Model, >1000 | 3 |
| Thermal Resistance, SOIC-16 | θJA |  | 126 |  | °C/W | SOIC-16, FR4 board per JESD51-7 | 3 |
| Power Dissipation in Still Air at 25°C | PD |  |  | 995 | mW | SOIC-16 | 3 |
| DC Supply Voltage (HC) | VCC | 2 |  | 6 | V | MC74HC | 3 |
| DC Input/Output Voltage (HC) | VIN, VOUT | 0 |  |  | V | 0 to VCC | 3 |
| Operating Free-Air Temperature (HC) | TA | -55 |  | 125 | °C | MC74HC | 3 |
| Input Rise or Fall Time (HC) | tr, tf | 0 |  | 1000 | ns | VCC = 2.0 V | 3 |
| Input Rise or Fall Time (HC) | tr, tf | 0 |  | 500 | ns | VCC = 4.5 V | 3 |
| Input Rise or Fall Time (HC) | tr, tf | 0 |  | 400 | ns | VCC = 6.0 V | 3 |
| Minimum High-Level Input Voltage | VIH | 3.15 |  |  | V | VCC = 4.5 V, VOUT = 0.1 V or VCC - 0.1 V, /IOUT/ ≤ 20 µA, -55 to 25°C | 4 |
| Maximum Low-Level Input Voltage | VIL |  |  | 1.35 | V | VCC = 4.5 V, VOUT = 0.1 V or VCC - 0.1 V, /IOUT/ ≤ 20 µA, -55 to 25°C | 4 |
| Minimum High-Level Output Voltage, QA-QH | VOH | 4.4 |  |  | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 20 µA, -55 to 25°C | 4 |
| Minimum High-Level Output Voltage, QA-QH | VOH | 3.98 |  |  | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 6.0 mA, -55 to 25°C | 4 |
| Minimum High-Level Output Voltage, QA-QH | VOH | 3.7 |  |  | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 6.0 mA, ≤125°C | 4 |
| Low-Level Output Voltage, QA-QH | VOL |  |  | 0.1 | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 20 µA, -55 to 25°C | 4 |
| Low-Level Output Voltage, QA-QH | VOL |  |  | 0.26 | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 6.0 mA, -55 to 25°C | 4 |
| Low-Level Output Voltage, QA-QH | VOL |  |  | 0.4 | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 6.0 mA, ≤125°C | 4 |
| Minimum High-Level Output Voltage, SQH | VOH | 3.98 |  |  | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 4.0 mA, -55 to 25°C | 4 |
| Low-Level Output Voltage, SQH | VOL |  |  | 0.26 | V | VCC = 4.5 V, VIN = VIH or VIL, /IOUT/ ≤ 4.0 mA, -55 to 25°C | 4 |
| Maximum Input Leakage Current | IIN | -0.1 |  | 0.1 | µA | VCC = 6.0 V, VIN = VCC or GND, -55 to 25°C | 4 |
| Maximum Input Leakage Current | IIN | -1 |  | 1 | µA | VCC = 6.0 V, VIN = VCC or GND, ≤125°C | 4 |
| Maximum Three-State Leakage Current | IOZ | -0.5 |  | 0.5 | µA | VCC = 6.0 V, output in high-impedance, VIN = VIL or VIH, VOUT = VCC or GND, -55 to 25°C | 4 |
| Maximum Three-State Leakage Current | IOZ | -10 |  | 10 | µA | VCC = 6.0 V, output in high-impedance, VIN = VIL or VIH, VOUT = VCC or GND, ≤125°C | 4 |
| Maximum Quiescent Supply Current (per Package) | ICC |  |  | 4 | µA | VCC = 6.0 V, VIN = VCC or GND, -55 to 25°C | 4 |
| Maximum Quiescent Supply Current (per Package) | ICC |  |  | 160 | µA | VCC = 6.0 V, VIN = VCC or GND, ≤125°C | 4 |
| Maximum Clock Frequency | fmax | 30 |  |  | MHz | VCC = 4.5 V, 50% duty cycle, -55 to 25°C | 5 |
| Maximum Clock Frequency | fmax | 20 |  |  | MHz | VCC = 4.5 V, 50% duty cycle, ≤125°C | 5 |
| Max Propagation Delay, Shift Clock to SQH | tPLH, tPHL |  |  | 28 | ns | VCC = 4.5 V, -55 to 25°C | 5 |
| Max Propagation Delay, Shift Clock to SQH | tPLH, tPHL |  |  | 42 | ns | VCC = 4.5 V, ≤125°C | 5 |
| Max Propagation Delay, Reset to SQH | tPHL |  |  | 29 | ns | VCC = 4.5 V, -55 to 25°C | 5 |
| Max Propagation Delay, Latch Clock to QA-QH | tPLH, tPHL |  |  | 28 | ns | VCC = 4.5 V, -55 to 25°C | 5 |
| Max Propagation Delay, Output Enable to QA-QH (disable) | tPLZ, tPHZ |  |  | 30 | ns | VCC = 4.5 V, -55 to 25°C | 5 |
| Max Propagation Delay, Output Enable to QA-QH (enable) | tPZL, tPZH |  |  | 27 | ns | VCC = 4.5 V, -55 to 25°C | 5 |
| Max Output Transition Time, QA-QH | tTLH, tTHL |  |  | 12 | ns | VCC = 4.5 V, -55 to 25°C | 5 |
| Max Output Transition Time, SQH | tTLH, tTHL |  |  | 15 | ns | VCC = 4.5 V, -55 to 25°C | 5 |
| Maximum Input Capacitance | Cin |  |  | 10 | pF |  | 5 |
| Maximum Three-State Output Capacitance, QA-QH | Cout |  |  | 15 | pF | Output in high-impedance state | 5 |
| Power Dissipation Capacitance (per Package) | CPD |  | 300 |  | pF | Typical @ 25°C, VCC = 5.0 V | 5 |
| Minimum Setup Time, Serial Data Input A to Shift Clock | tsu |  |  | 10 | ns | VCC = 4.5 V, 25°C to -55°C (minimum value 10) | 6 |
| Minimum Setup Time, Shift Clock to Latch Clock | tsu |  |  | 15 | ns | VCC = 4.5 V, 25°C to -55°C (minimum value 15) | 6 |
| Minimum Hold Time, Shift Clock to Serial Data Input A | th |  |  | 5 | ns | VCC = 4.5 V, 25°C to -55°C (minimum value 5.0) | 6 |
| Minimum Recovery Time, Reset Inactive to Shift Clock | trec |  |  | 10 | ns | VCC = 4.5 V, 25°C to -55°C (minimum value 10) | 6 |
| Minimum Pulse Width, Reset | tw |  |  | 12 | ns | VCC = 4.5 V, 25°C to -55°C (minimum value 12) | 6 |
| Minimum Pulse Width, Shift Clock | tw |  |  | 10 | ns | VCC = 4.5 V, 25°C to -55°C (minimum value 10) | 6 |
| Minimum Pulse Width, Latch Clock | tw |  |  | 10 | ns | VCC = 4.5 V, 25°C to -55°C (minimum value 10) | 6 |
| Maximum Input Rise and Fall Times | tr, tf |  |  | 500 | ns | VCC = 4.5 V | 6 |

## CAD (KiCad official)

- Symbol: `MC74HC595ADG`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `mc74hc595adg-etched.step` / `mc74hc595adg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mc74hc595adg.step` / `mc74hc595adg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/mc74hc595a-d.pdf) (18 pp, sha256 `1c7868e4947a2f5b`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mc74hc595adg-datasheet.pdf)