component
MC74HC589ADTR2G
Public Made by Adomby adom
onsemi Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownMC74HC589ADTR2G
onsemi · Shift Registers · TSSOP-16
MC74HC589ADTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Parallel data input B is stored in the data latch on the rising edge of Latch Clock. |
| 2 | C | input | Parallel data input C is stored in the data latch on the rising edge of Latch Clock. |
| 3 | D | input | Parallel data input D is stored in the data latch on the rising edge of Latch Clock. |
| 4 | E | input | Parallel data input E is stored in the data latch on the rising edge of Latch Clock. |
| 5 | F | input | Parallel data input F is stored in the data latch on the rising edge of Latch Clock. |
| 6 | G | input | Parallel data input G is stored in the data latch on the rising edge of Latch Clock. |
| 7 | H | input | Parallel data input H is stored in the data latch on the rising edge of Latch Clock. |
| 8 | GND | power_in | Ground reference pin for the device (GND = pin 8); all voltages are referenced to this pin. |
| 9 | QH | tri_state | Serial data output from the last shift-register stage; this 3-state output goes to high impedance when Output Enable is high. |
| 10 | Output Enable | input | Active-low output enable: a low level enables QH, and a high level forces QH into the high-impedance state without affecting the latch or shift register. |
| 11 | Shift Clock | input | Serial shift clock: a low-to-high transition shifts the serial input SA into the shift register and shifts stage H out to QH. |
| 12 | Latch Clock | input | Data latch clock: a low-to-high transition loads the parallel data on inputs A-H into the data latch. |
| 13 | Serial Shift/Parallel Load | input | Shift register mode control: a high level allows serial shifting, while a low level loads parallel data from the data latch into the shift register. |
| 14 | SA | input | Serial data input that is shifted into the shift register on the rising edge of Shift Clock when Serial Shift/Parallel Load is high and ignored when it is low. |
| 15 | A | input | Parallel data input A is stored in the data latch on the rising edge of Latch Clock. |
| 16 | VCC | power_in | Positive supply pin (VCC = pin 16); the recommended DC supply range is 2.0 V to 6.0 V referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Clock Frequency (50% Duty Cycle), VCC=2.0 V | fmax | 4 | MHz | VCC 2.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle), VCC=3.0 V | fmax | 8 | MHz | VCC 3.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle), VCC=4.5 V | fmax | 20 | MHz | VCC 4.5 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Clock Frequency (50% Duty Cycle), VCC=6.0 V | fmax | 24 | MHz | VCC 6.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Propagation Delay, Latch Clock to QH, VCC=2.0 V | tPLH, tPHL | 275 | ns | VCC 2.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 2 and 9 | 4 | ||
| Maximum Propagation Delay, Latch Clock to QH, VCC=3.0 V | tPLH, tPHL | 125 | ns | VCC 3.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 2 and 9 | 4 | ||
| Maximum Propagation Delay, Latch Clock to QH, VCC=4.5 V | tPLH, tPHL | 60 | ns | VCC 4.5 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 2 and 9 | 4 | ||
| Maximum Propagation Delay, Latch Clock to QH, VCC=6.0 V | tPLH, tPHL | 50 | ns | VCC 6.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 2 and 9 | 4 | ||
| Maximum Propagation Delay, Shift Clock to QH, VCC=2.0 V | tPLH, tPHL | 240 | ns | VCC 2.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Propagation Delay, Shift Clock to QH, VCC=3.0 V | tPLH, tPHL | 160 | ns | VCC 3.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Propagation Delay, Shift Clock to QH, VCC=4.5 V | tPLH, tPHL | 48 | ns | VCC 4.5 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Propagation Delay, Shift Clock to QH, VCC=6.0 V | tPLH, tPHL | 40 | ns | VCC 6.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 3 and 9 | 4 | ||
| Maximum Propagation Delay, Output Enable to QH (high-impedance), VCC=2.0 V | tPLZ, tPHZ | 200 | ns | VCC 2.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 4 and 10 | 4 | ||
| Maximum Propagation Delay, Output Enable to QH (high-impedance), VCC=3.0 V | tPLZ, tPHZ | 130 | ns | VCC 3.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 4 and 10 | 4 | ||
| Maximum Propagation Delay, Output Enable to QH (high-impedance), VCC=4.5 V | tPLZ, tPHZ | 40 | ns | VCC 4.5 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 4 and 10 | 4 | ||
| Maximum Propagation Delay, Output Enable to QH (high-impedance), VCC=6.0 V | tPLZ, tPHZ | 30 | ns | VCC 6.0 V, CL 50 pF, tr=tf 6 ns, 125C column, Figures 4 and 10 | 4 | ||
| Maximum Input Capacitance | Cin | 10 | pF | 4 | |||
| Maximum Three-State Output Capacitance (output in high-impedance state) | Cout | 15 | pF | Output in high-impedance state | 4 | ||
| Minimum High-Level Input Voltage, VCC=2.0 V | VIH | 1.5 | V | VCC 2.0 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Minimum High-Level Input Voltage, VCC=3.0 V | VIH | 2.1 | V | VCC 3.0 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Minimum High-Level Input Voltage, VCC=4.5 V | VIH | 3.15 | V | VCC 4.5 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Minimum High-Level Input Voltage, VCC=6.0 V | VIH | 4.2 | V | VCC 6.0 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Maximum Low-Level Input Voltage, VCC=2.0 V | VIL | 0.5 | V | VCC 2.0 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Maximum Low-Level Input Voltage, VCC=3.0 V | VIL | 0.9 | V | VCC 3.0 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Maximum Low-Level Input Voltage, VCC=4.5 V | VIL | 1.35 | V | VCC 4.5 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Maximum Low-Level Input Voltage, VCC=6.0 V | VIL | 1.8 | V | VCC 6.0 V, Vout = 0.1 V or VCC - 0.1 V, /Iout/ <= 20 uA, 125C column | 3 | ||
| Minimum High-Level Output Voltage, /Iout/ <= 20 uA, VCC=2.0 V | VOH | 1.9 | V | VCC 2.0 V, Vin = VIH or VIL, /Iout/ <= 20 uA, 125C column | 3 | ||
| Minimum High-Level Output Voltage, /Iout/ <= 20 uA, VCC=4.5 V | VOH | 4.4 | V | VCC 4.5 V, Vin = VIH or VIL, /Iout/ <= 20 uA, 125C column | 3 | ||
| Minimum High-Level Output Voltage, /Iout/ <= 20 uA, VCC=6.0 V | VOH | 5.9 | V | VCC 6.0 V, Vin = VIH or VIL, /Iout/ <= 20 uA, 125C column | 3 | ||
| Minimum High-Level Output Voltage, /Iout/ <= 2.4 mA, VCC=3.0 V | VOH | 2.2 | V | VCC 3.0 V, Vin = VIH or VIL, /Iout/ <= 2.4 mA, 125C column | 3 | ||
| Minimum High-Level Output Voltage, /Iout/ <= 6.0 mA, VCC=4.5 V | VOH | 3.7 | V | VCC 4.5 V, Vin = VIH or VIL, /Iout/ <= 6.0 mA, 125C column | 3 | ||
| Minimum High-Level Output Voltage, /Iout/ <= 7.8 mA, VCC=6.0 V | VOH | 5.2 | V | VCC 6.0 V, Vin = VIH or VIL, /Iout/ <= 7.8 mA, 125C column | 3 | ||
| Maximum Low-Level Output Voltage, /Iout/ <= 20 uA, VCC=2.0 V | VOL | 0.1 | V | VCC 2.0 V, Vin = VIH, /Iout/ <= 20 uA, 125C column | 3 | ||
| Maximum Low-Level Output Voltage, /Iout/ <= 20 uA, VCC=4.5 V | VOL | 0.1 | V | VCC 4.5 V, Vin = VIH, /Iout/ <= 20 uA, 125C column | 3 | ||
| Maximum Low-Level Output Voltage, /Iout/ <= 20 uA, VCC=6.0 V | VOL | 0.1 | V | VCC 6.0 V, Vin = VIH, /Iout/ <= 20 uA, 125C column | 3 | ||
| Maximum Low-Level Output Voltage, /Iout/ <= 2.4 mA, VCC=3.0 V | VOL | 0.4 | V | VCC 3.0 V, Vin = VIH or VIL, /Iout/ <= 2.4 mA, 125C column | 3 | ||
| Maximum Low-Level Output Voltage, /Iout/ <= 6.0 mA, VCC=4.5 V | VOL | 0.4 | V | VCC 4.5 V, Vin = VIH or VIL, /Iout/ <= 6.0 mA, 125C column | 3 | ||
| Maximum Low-Level Output Voltage, /Iout/ <= 7.8 mA, VCC=6.0 V | VOL | 0.4 | V | VCC 6.0 V, Vin = VIH or VIL, /Iout/ <= 7.8 mA, 125C column | 3 | ||
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC 6.0 V, Vin = VCC or GND, 125C column | 3 | |
| Maximum Three-State Leakage Current | IOZ | -10 | 10 | µA | VCC 6.0 V, output in high-impedance state, Vin = VIL or VIH, Vout = VCC or GND, 125C column | 3 | |
| Maximum Quiescent Supply Current (per package) | ICC | 160 | µA | VCC 6.0 V, Vin = VCC or GND, Iout = 0 µA, 125C column | 3 | ||
| DC Supply Voltage (Referenced to GND) | VCC | -0.5 | 7 | V | 2 | ||
| DC Input Voltage (Referenced to GND) | Vin | -0.5 | V | Upper limit printed as VCC + 0.5 V | 2 | ||
| DC Output Voltage (Referenced to GND) | Vout | -0.5 | V | Upper limit printed as VCC + 0.5 V | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | per pin | 2 | |
| DC Output Current, per Pin | Iout | -35 | 35 | mA | per pin | 2 | |
| DC Supply Current, VCC and GND Pins | ICC | -75 | 75 | mA | VCC and GND pins | 2 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Junction Temperature Under Bias | TJ | 150 | °C | Under bias | 2 | ||
| Latchup Performance Above VCC and Below GND | ILatchup | -300 | 300 | mA | At 85°C (JESD78) | 2 | |
| ESD Withstand Voltage, Human Body Model | VESD | 4000 | V | Human Body Model, EIA/JESD22-A114-A; datasheet prints > 4000 V | 2 | ||
| Power Dissipation in Still Air at 85°C, TSSOP | PD | 450 | mW | TSSOP package, still air at 85°C | 2 | ||
| Thermal Resistance, Junction-to-Ambient, TSSOP | RθJA | 148 | °C/W | TSSOP package | 2 | ||
| DC Supply Voltage (Referenced to GND) | VCC | 2 | 6 | V | 2 | ||
| DC Input Voltage, DC Output Voltage (Referenced to GND) | Vin, Vout | 0 | V | Upper limit printed as VCC | 2 | ||
| Operating Temperature, All Package Types | TA | -55 | 125 | °C | 2 | ||
| Input Rise and Fall Time, VCC=2.0 V | tr, tf | 0 | 1000 | ns | VCC 2.0 V, Figure 2 | 2 | |
| Input Rise and Fall Time, VCC=3.0 V | tr, tf | 0 | 800 | ns | VCC 3.0 V, Figure 2 | 2 | |
| Input Rise and Fall Time, VCC=4.5 V | tr, tf | 0 | 500 | ns | VCC 4.5 V, Figure 2 | 2 | |
| Input Rise and Fall Time, VCC=6.0 V | tr, tf | 0 | 400 | ns | VCC 6.0 V, Figure 2 | 2 |
CAD (KiCad official)
- Symbol:
MC74HC589ADTR2G - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
mc74hc589adtr2g-etched.step/mc74hc589adtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74hc589adtr2g.step/mc74hc589adtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (12 pp, sha256
ddab43d7484d270f, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).